Master-Slave Flash Memory Reset Busy State Alignment
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Solution Overview
Problem
In semiconductor memory devices with stacked memory chips, inconsistencies in busy states between the master and slave memory chips can occur, leading to operational issues where the slave chip remains busy while the master chip is not, causing failed operations even when the slave chip is selected by the host computer.
Innovation Solution
A semiconductor memory device with a master and at least one slave memory chip, where the master chip sets flag information upon selection and controls data readout to ensure the time required for data setting in a register is longer than the reset time of the slave chip, preventing premature busy state deactivation of the master chip.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the master side memory chip performs reset operation and reads data from memory cell array, then the data can be set in register, but the time required for data setting may be shorter than the reset time of slave chip, causing busy state inconsistency
Solution Approach 1:
The control component delays the readout of reset data from the master chip until after the slave chip's reset operation is complete. This preliminary timing adjustment ensures that the master chip remains in a busy state throughout the entire reset period, preventing premature busy state deactivation and ensuring consistent operation across both chips.
2Ease of operation
If the slave side memory chip is selected and a specific command is inputted, then the flag information is set, but the master chip may exit busy state before slave chip completes reset, causing operational failure
Solution Approach 1:
The detecting component continuously monitors whether a reset command has been inputted when flag information is set. This feedback mechanism allows the control component to adjust the timing of data readout dynamically, ensuring that the master chip's busy state is maintained until the slave chip's reset is complete, thereby preventing operational failures.
3Loss of time
If the master chip reads data quickly from memory cell array, then the register can be set faster, but the master chip's busy state may end before slave chip reset is complete
Solution Approach 1:
The system dynamically adjusts the timing of the data readout operation based on the reset command detection and slave chip status. The control component modifies the readout timing to ensure that the master chip remains in a busy state for the required duration, balancing the data setting speed with the need for busy state alignment between chips.
Data Source
AI summary
The disclosure prevents inconsistencies in a busy state between a master side memory chip and a slave side memory chip during a reset operation. A flash memory device (100) of the disclosure includes a master side memory chip (200) and at least one slave side memory chip (300). A controller (230) of the master side memory chip (200) selects the master side memory chip or the slave side memory chip based on an externally inputted address, and performs a reset of the selected memory chip when a reset command is inputted. The data read from a specific area of a memory cell array of the master side memory chip is set in a register. The controller (230) controls a readout of the reset in a manner that time required for setting the data of the register is longer than time required for the reset of the selected memory chip.