Multichip Flash Memory Reset Circuit for Stable Chip Selection
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Solution Overview
Problem
In multichip nonvolatile semiconductor memory systems, variations in the threshold voltage of power-on reset circuits can lead to inconsistent chip selection and operation failures due to power supply noise, causing all memory chips to become unselected and unable to perform operations requiring chip addresses.
Innovation Solution
The implementation of a power-on reset circuit with a switching circuit that adjusts the voltage dividing ratio and switch element configuration for each memory chip, ensuring that only the intended chip is selected and operated upon power-on, while others remain unselected, thereby reducing the impact of threshold voltage variations and power supply noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a power-on reset circuit with fixed voltage dividing ratio is used in multichip memory systems, then the circuit structure is simple, but threshold voltage variations and power supply noise cause inconsistent chip selection and operation failures
Solution Approach 1:
The patent applies dynamics by making the voltage dividing ratio adjustable through a switching circuit that can dynamically change the resistance values in the voltage dividing circuit. This allows the power-on reset circuit to adapt its detection threshold according to different chip configurations, resolving the contradiction between reliability and fixed structure by introducing controlled variability.
Solution Approach 2:
The patent changes the electrical parameters (resistance values) of the voltage dividing circuit based on the number of memory chips connected. By adjusting the voltage dividing ratio according to the actual chip configuration, the system maintains reliable chip selection across different multichip setups without requiring a completely different circuit architecture for each configuration.
2Reliability
If the voltage dividing ratio is adjusted for each memory chip to prevent noise interference, then chip selection reliability improves, but the circuit configuration and control complexity increases
Solution Approach 1:
The patent segments the voltage dividing circuit into multiple adjustable sections with different resistance values. By dividing the circuit into controllable segments that can be selectively activated, the system achieves precise voltage threshold adjustment without requiring a completely separate circuit for each chip, thereby reducing overall complexity while maintaining detection accuracy.
Solution Approach 2:
The switching circuit serves multiple functions: it adjusts the voltage dividing ratio, controls the power-on reset signal generation, and adapts to different chip configurations. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby improving reliability without proportionally increasing overall system complexity.
3Ease of manufacture
If all memory chips use the same power-on reset circuit configuration, then manufacturing is simple, but power supply noise can cause all chips to become unselected simultaneously
Solution Approach 1:
The patent applies local quality by giving each memory chip a power-on reset circuit with locally adjusted characteristics. Each chip's circuit is configured with specific resistance values adapted to its position and connection in the multichip system, creating local variations that prevent simultaneous failure while maintaining overall system manufacturability through standardized modular design.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration ensures that the nonvolatile semiconductor memory system can perform desired operations even when power supply noise is present, maintaining chip selection and preventing system-wide failures during power fluctuations.
Implementation Method 1
a first voltage dividing resistor having one end connected to a power supply; a second voltage dividing resistor connected between an other end of the first voltage dividing resistor and ground
Implementation Method 2
a PMOS transistor having a source connected to the power supply and a gate fed with a voltage corresponding to a voltage on a first contact between the first voltage dividing resistor and the second voltage dividing resistor
Data Source
AI summary
A nonvolatile semiconductor memory has a first memory chip set so as to be operated by specifying the chip address upon reset; and a second memory chip set so as not to be specified by the chip address and not to be operated upon reset, the first memory chip and the second memory chip each comprising a power-on reset circuit which detects a power supply voltage after power-on and outputs a reset signal for resetting an operation when the power supply voltage is equal to or higher than a predetermined value.