Flash Memory Data Writing Method for Response Time Reduction

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Solution Overview

Problem

Flash memory systems with large erasing units face prolonged response times due to excessive block moving times, leading to potential time-out issues, which hinder their use in modern flash storage systems.

Innovation Solution

A data writing method that divides flash memory into data, spare, and special areas, allowing update data to be written directly into the special area and moving only a portion of valid data during each command, thereby reducing the response time by optimizing data movement and erasure processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of stationary object

If the erasing unit size is increased to satisfy large storage volume requirements, then the storage capacity is improved, but the response time for data writing commands exceeds acceptable limits due to excessive block moving time

Engineering Contradiction:
Improvestorage capacityVSAvoidresponse time
Core Design Contradiction:
Volume of stationary objectVSLoss of time

Solution Approach 1:

The patent segments the data movement process by introducing a special area that stores only partial valid data (e.g., first half or last half of data pages) during the erasing unit write process. This segmentation allows the write operation to complete without waiting for the entire large erasing unit to be moved, significantly reducing response time while maintaining data integrity through subsequent completion operations.

Inventive Principle:
Principle #1Segmentation

2Volume of stationary object

If the erasing unit size is increased to meet customer demand for large storage media, then the volume of storage media is improved, but the flash memory cannot be used in latest flash storage systems due to excessive block moving time

Engineering Contradiction:
Improvestorage media volumeVSAvoidcompatibility with flash storage systems
Core Design Contradiction:
Volume of stationary objectVSAdaptability or versatility

Solution Approach 1:

The patent introduces a special area as an intermediary storage region between the data area and the erasing unit. This special area temporarily holds partial valid data during write operations, acting as a buffer that decouples the write command response from the lengthy data movement process, thereby enabling compatibility with modern flash storage systems that require fast response times.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Reliability

If all valid data in the erasing unit is moved before writing, then data integrity is ensured, but the response time for data writing commands becomes excessively long

Engineering Contradiction:
Improvedata integrityVSAvoidresponse time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent performs preliminary action by storing partial valid data in the special area before the write operation completes. This preliminary storage of essential data portions allows the system to acknowledge write commands immediately while ensuring data integrity through subsequent completion operations that finish moving the remaining data and update mappings.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8131911B2Data writing method, and flash storage system and controller using the same
Publication Date: 2012.03.06 PHISON ELECTRONICS
  • US8131911B2 patent drawing
  • US8131911B2 patent drawing
  • US8131911B2 patent drawing

AI summary

A data writing method, and a flash storage system and a controller using the same are provided. The method includes grouping the physical blocks of a flash memory into the physical blocks of a data area, a spare area and a special area. The method also includes writing the update data into the corresponding physical block of the special area when the update data is the single accessing unit. The method may include moving a part of valid data in a physical block mapping a logical block where the update data is belonged into a physical block of the spare area during each data writing command. Accordingly, it is possible to reduce the response time for each data writing command, thereby preventing a time-out problem caused by a flash memory having a large erasing unit configured at the flash storage system.