Flash Memory Cache Read Logic for Reverse Data Access
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Solution Overview
Problem
Existing flash memory devices lack the capability to perform cache read operations for previous data pages, limiting system throughput when data needs to be read in reverse order, as they are not configured to handle decremented page addresses and require explicit address specification for each operation.
Innovation Solution
A flash memory device with a logic mechanism responsive to 'normal' and 'reverse' cache read commands, allowing data pages to be retrieved with decremented addresses without explicit specification, utilizing two buffers for simultaneous data transfer and enabling reading of previous data pages by decrementing addresses between the page and cache buffers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a cache buffer is implemented to enable simultaneous data transfer and increase throughput, then the system throughput is improved, but the device complexity increases
Solution Approach 1:
The patent divides the data buffer into two separate buffers: a page buffer for holding pages read from the memory array and a cache buffer for holding pages transferred to the host. This segmentation allows simultaneous operations to occur in parallel, with the page buffer handling reads from the array while the cache buffer handles transfers to the host, thereby increasing throughput without requiring complex integrated buffer management
Solution Approach 2:
The patent implements preliminary action by allowing the host to issue a command to read a next page from the memory array before the current page transfer to the host is complete. The page buffer is used to hold the next page in advance, and when ready, it can be transferred to the cache buffer or directly to the host without waiting for the current operation to finish, enabling overlapping operations and increasing throughput
2Productivity
If the flash memory device uses sequential page reading with a cache buffer, then the throughput is improved, but the adaptability to reverse order reading is reduced
Solution Approach 1:
The patent introduces dynamic address incrementing capability where the address increment value can be configured based on the reading direction. For forward reading, the address increments by +1, while for reverse reading, the address increments by -1. This dynamic adjustment allows the same cache buffer mechanism to adapt to both sequential forward reading and reverse order reading requirements, maintaining high throughput in both modes
Solution Approach 2:
The patent makes the cache buffer mechanism universal by enabling it to handle both forward sequential reading and reverse order reading through a single unified architecture. The same page buffer and cache buffer structure, along with the address incrementing logic, can accommodate both reading directions, eliminating the need for separate mechanisms and maintaining adaptability while preserving throughput benefits
3Manufacturing precision
If explicit address specification is required for each read operation, then the manufacturing precision is improved, but the ease of operation is reduced
Solution Approach 1:
The patent implements self-service by having the system automatically manage address incrementing based on the reading direction. When forward reading is detected, the address automatically increments by +1; when reverse reading is detected, the address automatically increments by -1. This eliminates the need for the host to manually specify each address, reducing operational complexity while maintaining precise address specification through automatic address management
Data Source
AI summary
A flash memory device includes an array of memory cells for storing data pages, one or more buffers for retrieving the data pages and a logic mechanism that, responsive to a plurality of commands, transfers the data pages between the buffers and a host. Each command subsequent to a first command instructs retrieval of a data page whose address either precedes, or exceeds by more than 1, the address of the data page retrieved by the immediately preceding command, and at least one command does not explicitly specify the address of its retrieved data page. Another similar flash memory device uses two buffers to implement cache reads of data pages whose addresses are specified arbitrarily in the commands subsequent to the first command.