Alternate Row Programming for Flash Memory Coupling
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Solution Overview
Problem
The challenge in non-volatile semiconductor memory, particularly in multi-state flash memory devices, is the floating gate to floating gate coupling phenomenon, which leads to erroneous readings due to shifts in apparent charge storage, exacerbated by shrinking memory cell sizes and increased coupling between adjacent cells, causing memory cells to shift from allowed to forbidden threshold voltage ranges.
Innovation Solution
A programming sequence is implemented where certain word lines are programmed in an alternate manner to avoid subsequent floating gate to floating gate coupling, allowing for accurate reading without offsets, and managing circuitry determines offsets based on charge levels in adjacent cells to compensate for coupling effects during read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are programmed in conventional sequential order, then programming efficiency is maintained, but floating gate to floating gate coupling causes threshold voltage shifts leading to read errors
Solution Approach 1:
The patent segments the programming process into distinct phases: a first programming phase that programs selected memory cells while leaving adjacent cells unprogrammed, and a second programming phase that programs the previously skipped adjacent cells. This segmentation prevents coupling-induced threshold voltage shifts during reading while maintaining overall programming efficiency through parallel phase execution.
Solution Approach 2:
The patent applies preliminary action by programming certain word lines (e.g., even-numbered word lines) first before programming adjacent word lines (e.g., odd-numbered word lines). This preliminary programming sequence ensures that when reading the first-programmed word lines, adjacent word lines remain unprogrammed and thus do not cause coupling effects that would shift threshold voltages and cause read errors.
2Quantity of substance
If memory cell size is reduced to increase density, then storage capacity increases, but coupling between adjacent cells increases causing threshold voltage shifts
Solution Approach 1:
The patent segments the memory array programming into phases where adjacent word lines are programmed at different times. This temporal segmentation effectively isolates the coupling effect, allowing high-density cell arrangements to be programmed and read without threshold voltage shifts caused by adjacent cell coupling, even as cell sizes continue to shrink.
3Quantity of substance
If multi-state memory is used to increase capacity, then storage density increases, but allowed threshold voltage ranges become narrower making cells more susceptible to coupling effects
Solution Approach 1:
The patent applies preliminary action by programming word lines in a specific sequence where certain word lines are programmed before adjacent word lines. When reading the preliminary-programmed word lines, the adjacent word lines remain unprogrammed and do not cause coupling effects. This preserves the narrow threshold voltage ranges required for multi-state memory reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the impact of floating gate to floating gate coupling, ensuring accurate data retrieval by minimizing margin shifts and maintaining reliable read margins, even in densely programmed memory cells, thereby enhancing the reliability and precision of multi-state flash memory devices.
Implementation Method 1
Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory cell is raised
Implementation Method 2
A program voltage is applied to the control gate and the bit line is grounded. Electrons from the channel are injected into the floating gate
Implementation Method 3
Shifts in the apparent charge stored on a floating gate can occur because of the coupling of an electric field based on the charge stored in adjacent floating gates
Data Source
AI summary
A set of storage elements is programmed beginning with a word line WLn adjacent a select gate line for the set. After programming the first word line, the next word line WLn+1 adjacent to the first word line is skipped and the next word line WLn+2 adjacent to WLn+1 is programmed. WLn+1 is then programmed. Programming continues according to the sequence {WLn+4, WLn+3, WLn+6, WLn+5, . . . } until all but the last word line for the set have been programmed. The last word line is then programmed. By programming in this manner, some of the word lines of the set (WLn+1, WLn+3, etc.) have no subsequently programmed neighboring word lines. The memory cells of these word lines will not experience any floating gate to floating gate coupling threshold voltage shift impact due to subsequently programmed neighboring memory cells. The word lines having no subsequently programmed neighbors are read without using offsets or compensations based on neighboring memory cells. The other word lines are read using compensations based on data states within both subsequently programmed neighboring word lines.