Flash Memory Sampling Circuit for Data Reliability
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Solution Overview
Problem
Nonvolatile flash memory devices, such as NAND Flash, face reliability issues due to lobe overlap and distribution changes over time, leading to increased errors and reduced effective working window, especially as the technology node shrinks and P/E cycles increase, necessitating advanced error correction and decoding methods.
Innovation Solution
Implementing a sampling circuit and processor within the semiconductor die to sample flash memory cells multiple times during gate voltage changes, determining data reliability based on sample differences, and using internal soft sampling to generate reliable data without additional threshold sampling times, thereby improving data reliability and reducing latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If advanced ECC and DSP algorithms are used to overcome errors, then data reliability is improved, but device complexity and processing overhead increase
Solution Approach 1:
The patent performs preliminary sampling of flash memory cells during the gate voltage change period before the read operation is complete. By capturing multiple samples during the voltage transition and determining reliability metrics in advance, the system prepares reliability information beforehand, reducing the need for complex post-read processing and enabling simpler decoding algorithms to achieve the same reliability levels.
2Reliability
If multiple samples are taken during gate voltage change, then data reliability is improved, but sampling time and latency increase
Solution Approach 1:
The patent takes multiple samples continuously during the gate voltage change period without interrupting the normal read operation flow. The sampling occurs naturally as the voltage transitions, utilizing the existing voltage change window to gather multiple data points. This continuous sampling approach extracts maximum reliability information from the available time window, improving data reliability without adding significant latency to the read operation.
3Device complexity
If internal soft sampling is implemented within the die, then decoding complexity is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent implements a sampling circuit that serves multiple functions: it samples flash memory cells during voltage changes, generates reliability metrics, and provides data for decoding operations. By integrating this multi-functional sampling circuit directly into the die, the system reduces the need for separate external sampling hardware and complex decoding logic, as the same circuit performs multiple critical functions, thereby simplifying the overall system architecture despite the added manufacturing complexity.
Data Source
AI summary
According to an embodiment of the invention there may be provided a non-transitory computer readable medium that stores instructions that once executed by a computer cause the computer to sample a flash memory cell that belongs to a die, by attempting, during a gate voltage change period, to change a value of a gate voltage of the flash memory cell from a first value to a second value; sampling, by a sampling circuit that belongs to the die, an output signal of the flash memory cell multiple times during the voltage gate change period to provide multiple samples; defining a given sample of the multiple samples as a data sample that represents data stored in the flash memory cell; and determining, by a processor that belongs to the die, a reliability of the data sample based on one or more samples of the multiple samples that differ from the given sample. The processor may belong to the sampling circuit or may not belong to the sampling circuit.