Flash Memory System SBC Mode Control
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Solution Overview
Problem
Flash memory devices, particularly multi-level cell (MLC) flash memory, have a limited lifespan due to higher stress on cells, leading to a shorter program-erase cycle limit, making them unsuitable for applications requiring frequent data programming and high data integrity, such as solid-state drives, where the cost of single-level cell (SLC) flash devices is prohibitive.
Innovation Solution
A method and system for controlling a multiple bit per cell (MBC) flash memory device to store data in a single bit per cell (SBC) or partial MBC storage mode, using a memory controller that issues program commands with a subset of virtual page addresses to manage storage modes and extend the device's lifespan by reducing stress on memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC flash memory is used to increase storage density and reduce cost, then storage capacity per chip is improved, but program-erase cycle lifespan deteriorates
Solution Approach 1:
The flash memory device is divided into multiple subdivisions (e.g., memory blocks or pages), each capable of operating in different storage modes. This segmentation allows the system to distribute data across multiple regions, enabling some subdivisions to operate in SLC mode for high-endurance applications while others operate in MLC mode for maximum capacity, thereby resolving the contradiction between storage density and lifespan at the system level.
Solution Approach 2:
The flash memory device dynamically switches between SLC and MLC storage modes based on operational requirements. The device can transition subdivisions between modes during operation, allowing it to adapt to varying workload demands - using SLC mode for frequent write operations requiring high endurance, and MLC mode for capacity-critical applications, thus achieving both high storage density and extended program-erase cycle lifespan.
2Reliability
If SLC flash memory is used to improve program-erase cycle lifespan and data integrity, then reliability is improved, but cost increases
Solution Approach 1:
Different subdivisions of the flash memory device are assigned different storage modes based on local requirements. Critical data requiring high endurance is stored in SLC-mode subdivisions, while non-critical data is stored in MLC-mode subdivisions. This local differentiation allows the system to achieve high reliability for important data without incurring the full cost of SLC memory across the entire device, thus resolving the cost-reliability contradiction.
Solution Approach 2:
The flash memory device is designed to perform multiple functions by supporting both SLC and MLC storage modes within the same physical device. This multi-functionality allows a single device to serve both high-endurance applications (using SLC mode) and high-capacity applications (using MLC mode), eliminating the need for separate SLC and MLC devices and reducing overall system cost while maintaining high reliability where needed.
3Quantity of substance
If MLC flash memory operates in full MBC mode to maximize storage capacity, then storage density is improved, but data integrity deteriorates
Solution Approach 1:
The flash memory device dynamically adjusts its storage mode for each subdivision based on data integrity requirements. When high data integrity is required, the device switches to SLC mode with enhanced verification and error correction. When maximum capacity is sufficient, it operates in MLC mode. This dynamic adaptation resolves the contradiction between storage capacity and data integrity by allowing the system to optimize for the appropriate parameter based on application needs.
Data Source
AI summary
A method and system for controlling an MBC configured flash memory device to store data in an SBC storage mode, or a partial MBC storage mode. In a full MBC storage mode, pages of data are programmed sequentially from a first page to an Nth page for each physical row of memory cells. Up to N virtual page addresses per row of memory cells accompany each page to be programmed for designating the virtual position of the page in the row. For SBC or partial MBC data storage, a flash memory controller issues program command(s) to the MBC memory device using less than the maximum N virtual page addresses for each row. The MBC memory device sequentially executes programming operations up to the last received virtual page address for the row.