Flash Memory Scrambling Without Flag Bits
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Solution Overview
Problem
Conventional NAND type flash memory technologies face reliability issues due to uneven data distribution and capacitive coupling between memory cells, requiring additional storage for flag bits to differentiate erased and programmed data, and incur extra time during data reading operations.
Innovation Solution
A semiconductor memory apparatus and method that scrambles data without using identification information, utilizing an encoding unit to determine whether input data is a predetermined bit string, and a decoding unit to descramble data without the need for flag bits, thereby eliminating the need for additional storage and reducing data read time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data scrambling is implemented to achieve ideal data distribution ratio, then data reliability is improved, but additional storage capacity is required for flag bits to identify erased and programmed data
Solution Approach 1:
The patent extracts the identification function from separate flag bits and integrates it into the data pattern recognition process. By detecting specific bit patterns (all 1s or all 0s) directly in the scrambled data, the system eliminates the need for dedicated flag bit storage while maintaining the ability to distinguish between erased and programmed states.
Solution Approach 2:
The scrambled data serves multiple functions simultaneously: it maintains ideal data distribution for reliability, encodes the erasure/programmed state information within the data pattern itself, and eliminates the need for separate identification storage. The data pattern recognition mechanism provides universal identification for both erased and programmed pages without requiring additional storage resources.
2Reliability
If flag bits are used to identify erased and programmed data, then data state identification is achieved, but data read time increases due to additional processing steps
Solution Approach 1:
The patent merges the data read operation with the state identification operation. By detecting data patterns (all 1s for erased pages, all 0s for programmed pages) during the normal data read process, the system combines what were previously separate operations into a single unified process, thereby eliminating additional processing time while maintaining accurate state identification.
Solution Approach 2:
The scrambled data itself provides the identification information needed for state detection. The data pattern (all 1s or all 0s) serves as its own identifier, eliminating the need for separate flag bits and their associated read processing. The data is self-identifying through its pattern characteristics.
3Reliability
If data is scrambled with random numbers to achieve uniform distribution, then capacitive coupling interference is reduced, but device complexity increases due to scrambling and descrambling circuits
Solution Approach 1:
The patent changes the data representation parameters through scrambling operations, transforming the original data into a scrambled form with uniform distribution characteristics. This parameter transformation reduces capacitive coupling interference by ensuring balanced 0 and 1 distribution across memory cells, thereby improving reliability while managing circuit complexity through efficient scrambling algorithms.
Data Source
AI summary
A semiconductor memory apparatus is provided. The semiconductor memory apparatus does not require additional identification information to perform data scrambling and improves the reliability, where the identification information is used to identify whether it is an erased data or a programmed data. A flash memory of the present disclosure includes a scrambling unit 120 scrambling data between an input/output buffer 110 and a page buffer 160. The scrambling unit 120 includes a writing encoder 200 and a reading decoder 220. When an input data is equal to a predetermined bit string, the writing encoder 200 skips the scrambling of the input data. When a read data of the page buffer 160 is equal to the predetermined bit string, the reading decoder 220 skips the descrambling of the read data.