Flash Memory Data Scrambling Using Logical Addresses
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Solution Overview
Problem
Flash memory systems face data pattern-dependent sensitivities and disturbance effects due to repetitive data patterns, which are not effectively addressed by existing data scrambling techniques, especially when used with on-chip copy operations, leading to performance and reliability issues.
Innovation Solution
Implementing data scrambling techniques within flash memory systems using logical addresses to generate a seed scrambling key, allowing on-chip copy operations while maintaining system performance and reliability, and storing scrambling key information in page headers for initialization and data retrieval.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data scrambling is implemented using physical memory addresses, then data pattern sensitivity is reduced, but on-chip copy operations fail due to key mismatch
Solution Approach 1:
The patent segments the address space into logical addresses separate from physical addresses. The scrambling key is generated from logical addresses (LBA, PBA) which remain unchanged during on-chip copy operations, while physical addresses can change. This segmentation allows the same scrambling key to be used before and after copy operations, resolving the key mismatch problem.
Solution Approach 2:
The patent introduces logical addresses as an intermediary between the data and the scrambling mechanism. Instead of using physical addresses directly for key generation, logical addresses serve as a stable reference that mediates the scrambling process, ensuring consistency even when physical locations change during copy operations.
2Adaptability or versatility
If data is read off-chip and rewritten to another location, then data relocation is achieved, but system performance and power consumption deteriorate
Solution Approach 1:
The patent enables the flash memory device to perform copy operations autonomously using on-chip copy functionality. The device copies data internally between physical locations without requiring external controller intervention, thus serving itself and eliminating the need to read data off-chip and rewrite it, improving performance and reducing power consumption.
3Reliability
If data scrambling is implemented, then program disturb effects are reduced, but system complexity increases
Solution Approach 1:
The patent changes the parameter used for scrambling key generation from physical addresses to logical addresses. This parameter change maintains the benefits of data scrambling (reducing program disturb effects) while simplifying the system, as logical addresses are already managed by the flash file system and do not require additional complex address translation mechanisms.
Data Source
AI summary
Data scrambling techniques implemented externally to a flash memory device are disclosed which can be used in concert with flash memory on-chip copy functionality operating internally to the flash device, thus supporting high performance copying operations. All the data stored in the flash may be scrambled, including headers and control structures. Robust file system operation may be achieved, including the capability to tolerate a power loss at any time, and yet be able to relocate data internally within the flash without having to de-scramble and then re-scramble the data. An exemplary hardware based solution has little or no impact on overall system performance, and may be implemented at very low incremental cost to increase overall system reliability. The data scrambling technique preferably uses a logical address, such as logical block address or logical page address, rather than a physical address, to determine a seed scrambling key.