Flash Memory Logical Sector Erasure Control

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Solution Overview

Problem

Flash memory experiences data garbling due to erasure disturbance, where frequent erasure causes unintended changes in threshold voltage of non-selected memory cells, leading to loss of storage information.

Innovation Solution

A memory control method that logically divides physical sectors into multiple sectors, performing batch erasure only when no writable logical sectors are present, thereby minimizing erasure stress and preventing data garbling.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If frequent erasure is performed in flash memory, then data can be updated regularly, but erasure disturbance causes threshold voltage changes in non-selected cells leading to data garbling

Engineering Contradiction:
Improvedata update frequencyVSAvoiddata integrity
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The memory device is divided into multiple physical sectors, each further divided into multiple logical sectors. This segmentation allows independent erasure of specific logical sectors without affecting others, enabling selective erasure that updates only necessary data regions while preserving other data, thus maintaining data integrity during frequent updates.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies different erasure strategies to different logical sectors based on their write status. Fully written logical sectors are erased in batch operations, while sectors with unwritten pages are excluded from erasure. This local differentiation ensures that erasure stress is applied only where necessary, preventing disturbance to non-selected cells while maintaining productivity.

Inventive Principle:
Principle #3Local quality

2Productivity

If batch erasure is performed on all logical sectors, then storage space is reclaimed efficiently, but erasure stress is applied to sectors that still contain writable data causing potential data loss

Engineering Contradiction:
Improvestorage reclamation efficiencyVSAvoiddata safety
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The erasure operation is made dynamic and adaptive based on the current state of logical sectors. The memory controller checks the write status of each logical sector and dynamically adjusts the erasure scope. Only logical sectors that are fully written are included in batch erasure operations, while sectors with unwritten pages are dynamically excluded, ensuring data safety while maintaining efficient storage reclamation.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system uses feedback from the write status of logical sectors to control erasure operations. Before performing batch erasure, the memory controller verifies that target logical sectors have no unwritten pages. This feedback mechanism ensures that erasure is only applied to sectors that are safe to erase, preventing data loss while efficiently reclaiming storage space.

Inventive Principle:
Principle #23Feedback

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the frequency of erasure stress, ensuring that erasure disturbance is avoided, and data integrity is maintained by applying erasure voltage only when necessary, thus preventing data loss.

Implementation Method 1

erasure disturbance means a change in the amount of charge held in a floating gate of a memory cell in a non-selected state due to a voltage applied to the memory cell in the non-selected state during deletion of a selected cell

Methodology Applied
Scientific EffectCharge removal through voltage application: Electrostatics

Data Source

PatentUS20230420057A1Memory control method
Publication Date: 2023.12.28 DENSO CORP
  • US20230420057A1 patent drawing
  • US20230420057A1 patent drawing
  • US20230420057A1 patent drawing

AI summary

A memory control method includes: writing data in at least one page that is a part of a plurality of logical sectors; erasing the data in at least one of the plurality of logical sectors; and controlling an operation for write and erasure in a memory to which an erasure voltage is applied in a physical sector including the plurality of logical sectors; and performing batch erasure for each of a plurality of logically divided physical sectors obtained by logically dividing the physical sector into at least two sectors.