Flash Memory Sector Fail Bit Detection
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Solution Overview
Problem
Conventional flash memory verification methods are inefficient in ensuring few bit failures per sector, leading to extended programming and erase cycles due to slow-to-program or defective memory cells not being concentrated within a sector, which worsens with increasing page sizes and manufacturing advancements.
Innovation Solution
A method of verifying memory cell states by determining the number of inadequately programmed or erased cells within each sector, setting a threshold for termination, and controlling ignored bits within each sector to increase the tolerance for slow-to-program or defective cells, thus reducing programming and erase sequence durations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory verification methods are used to ensure few bit failures per sector, then programming and erase cycles must be extended to verify all cells, but this increases the duration of programming and erase operations
Solution Approach 1:
The patent segments the verification process by dividing the page into multiple sectors and performing fail bit detection separately for each sector. This allows the system to terminate programming or erase operations early when a sector reaches its fail bit threshold, rather than verifying all cells in the entire page. The segmentation enables independent evaluation of each sector's verification status, resolving the contradiction between ensuring reliability and reducing operation duration.
Solution Approach 2:
The patent applies partial action by performing verification on only a portion of the memory cells (those within the current sector being evaluated) rather than all cells in the page. When the cumulative fail bit count for a sector reaches the threshold, the operation terminates prematurely, performing less than the full verification that would otherwise be required. This partial verification approach maintains acceptable reliability while significantly reducing programming and erase cycle durations.
2Quantity of substance
If page sizes are increased to improve storage capacity, then the number of memory cells per page increases, but this extends the time required for verification and reduces productivity
Solution Approach 1:
The patent segments large pages into multiple smaller sectors for independent verification. This allows fail bit detection to operate on a fine-grained basis within each sector, enabling early termination when thresholds are reached. Consequently, even as page sizes increase to improve storage capacity, the segmented verification approach maintains high productivity by avoiding unnecessary verification of all cells in large pages.
Solution Approach 2:
The patent introduces a new dimensional approach to verification by organizing memory cells into a hierarchical structure of pages and sectors. This dimensional organization allows verification to proceed sector-by-sector within pages, adding a granularity dimension that enables early termination. This resolves the contradiction by allowing large page sizes for capacity while maintaining fast verification through sector-level control.
3Reliability
If strict verification thresholds are applied to ensure high reliability, then fewer defective cells are tolerated, but this increases programming and erase cycle durations
Solution Approach 1:
The patent implements dynamic verification thresholds by allowing different sectors to have different fail bit thresholds based on their specific characteristics and error correction capabilities. This dynamic approach enables the system to maintain high reliability where needed while tolerating more defects in sectors where error correction can compensate, thereby reducing overall verification time without sacrificing data integrity.
Solution Approach 2:
The patent employs feedback mechanisms by continuously monitoring fail bit counts during programming or erase operations and comparing them against sector-specific thresholds. When thresholds are reached, the system provides feedback to terminate the operation. This feedback-driven approach ensures high reliability by enforcing strict thresholds where necessary while enabling early termination to reduce cycle durations when thresholds are met.
Data Source
AI summary
A flash memory device, and a method of operating the same, is disclosed. The array of the flash memory device is arranged in pages of memory cells, each page having memory cells associated into groups of memory cells within the page for purposes of fail bit detection in program verification. For example, these groups may correspond to sectors within the page. In a programming operation, the verify process determines whether each group of memory cells within the page has fewer than a selected ignore bit limit for the sector. If not, additional programming is required for the insufficiently programmed cells in the page. By applying a fail bit detection threshold for each of multiple groups within the page, the efficiency of error correction coding in the flash memory is improved. A similar verify and fail bit detection approach may be used in erase and soft programming operations.