Flash Memory Sector-Specific Fail Bit Detection
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Solution Overview
Problem
Conventional flash memory verification methods are inefficient in ensuring few bit failures per sector, leading to extended programming and erase cycles due to slow-to-program or defective memory cells not being concentrated within a sector, which worsens with increasing page sizes and manufacturing advancements.
Innovation Solution
Implementing sector-specific bit comparison circuitry to determine the number of memory cells not adequately programmed or erased within each sector, allowing for earlier termination of programming or erase operations and enhanced error correction coding efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional page-wide verification methods are used, then manufacturing yield is maintained, but programming and erase cycle duration is extended
Solution Approach 1:
The patent divides the verification process into sector-specific segments rather than performing uniform page-wide verification. Each sector is verified independently using sector-specific bit comparison circuitry, allowing the system to identify and terminate verification early when a sector is successfully programmed or erased, thereby reducing overall cycle duration while maintaining reliability through targeted verification of each sector.
Solution Approach 2:
The patent applies different verification strategies to different sectors within a page based on their specific programming or erase status. By using sector-specific bit comparison circuitry, the system tailors the verification process to local conditions in each sector, enabling early termination for successfully processed sectors while continuing verification for sectors that require additional cycles, thus optimizing both speed and reliability.
2Quantity of substance
If page sizes are increased to improve storage capacity, then data capacity is enhanced, but programming and erase cycle duration is further extended
Solution Approach 1:
The patent segments large pages into smaller sectors for independent verification. This allows the system to handle large storage capacities by processing and verifying sectors independently, enabling early termination of verification sequences when individual sectors are complete, thereby preventing the overall programming and erase duration from scaling linearly with page size increases.
Solution Approach 2:
The patent performs verification on only the necessary portions of each sector rather than requiring complete page-wide verification. By using sector-specific bit comparison to identify successfully programmed or erased sectors, the system applies partial verification action that is sufficient to ensure reliability while avoiding unnecessary verification cycles on already-completed sectors, thus reducing overall sequence duration despite increased page sizes.
3Reliability
If uniform verification thresholds are applied across all sectors, then manufacturing robustness is maintained, but error correction coding efficiency is reduced
Solution Approach 1:
The patent applies different verification thresholds and criteria to different sectors based on their specific characteristics and error correction coding requirements. By using sector-specific bit comparison circuitry, the system tailors verification strictness to local conditions, allowing more lenient thresholds for sectors with strong error correction capability while maintaining strict thresholds for sectors requiring higher reliability, thereby optimizing both manufacturing robustness and error correction efficiency.
Solution Approach 2:
The patent changes verification parameters such as threshold values and comparison criteria based on sector-specific conditions. By dynamically adjusting verification parameters for each sector rather than applying uniform thresholds, the system optimizes the balance between manufacturing robustness and error correction coding efficiency, allowing faster verification for sectors that can tolerate higher error rates while maintaining strict verification for sectors requiring higher reliability.
Data Source
AI summary
A flash memory device, and a method of operating the same, is disclosed. The array of the flash memory device is arranged in pages of memory cells, each page having memory cells associated into groups of memory cells within the page for purposes of fail bit detection in program verification. For example, these groups may correspond to sectors within the page. In a programming operation, the verify process determines whether each group of memory cells within the page has fewer than a selected ignore bit limit for the sector. If not, additional programming is required for the insufficiently programmed cells in the page. By applying a fail bit detection threshold for each of multiple groups within the page, the efficiency of error correction coding in the flash memory is improved. A similar verify and fail bit detection approach may be used in erase and soft programming operations.