Flash Memory Security Data Pattern Mitigating Charge Loss
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Solution Overview
Problem
Flash memory devices, particularly nonvolatile ones like EEPROM, face limitations in simultaneous read and write operations due to wear and tear on insulating layers, leading to reduced performance and data loss over time, especially when updating memory contents.
Innovation Solution
A flash memory device with a user data area and a security data area, where the security data area has a higher error correction capability, stores security data patterns with memory cells arranged between dummy data cells to mitigate charge loss and data reliability issues, using a program scheme that prevents data loss by surrounding security data with dummy data cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If flash memory devices perform multiple erasing operations, then data storage capacity is maintained, but insulating layer abrasion occurs leading to data loss and reduced reliability
Solution Approach 1:
The patent applies preliminary action by pre-programming security data patterns into the memory device during manufacturing, before the device is delivered to the user. This includes configuring specific memory cells with security data and arranging dummy data in predetermined patterns. This preliminary configuration establishes a baseline security state that protects against future wear-induced data loss without requiring subsequent erasing operations.
Solution Approach 2:
The patent changes the parameter of data organization by implementing a specific pattern where security data is interspersed with dummy data in alternating sequences. This parameter change in data arrangement allows the error correction unit to more effectively distinguish and protect security data from wear-induced errors, extending the operational lifespan while maintaining reliability.
2Reliability
If error correction capability is increased for security data, then data loss is reduced, but device complexity increases
Solution Approach 1:
The patent segments the memory device into distinct functional areas: a security data area with enhanced error correction capability and other memory areas with standard error correction. This segmentation allows the increased error correction capability to be applied only where needed for security data, rather than throughout the entire device, thereby limiting the increase in device complexity to only the necessary portions.
Solution Approach 2:
The patent applies local quality by providing different levels of error correction capability in different regions of the memory device. The security data area receives superior error correction resources and protection mechanisms, while other areas use standard error correction. This localized approach ensures high reliability for security data without unnecessarily increasing the complexity of the entire device.
3Reliability
If security data is stored in dedicated areas with dummy data surrounding it, then charge loss is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring the security data pattern during the manufacturing process, including the arrangement of security data and dummy data in alternating sequences. This preliminary configuration is performed as part of the initial device fabrication, allowing the charge-retention-optimized structure to be established without requiring additional complex manufacturing steps after device completion.
Data Source
AI summary
A flash memory device provided here comprises a user data area storing user data; and a security data area storing security data. The security data area stores a security data pattern in which first groups of memory cells storing security data are arranged respectively between second groups of memory cells storing dummy data.