Flash Memory Emulating EEPROM Random Access via Segmented Addressing
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Solution Overview
Problem
Conventional flash memory systems lack the random access characteristics of electrically-erasable programmable read-only memory (EEPROM), as they require erasing entire pages before writing, which is not suitable for applications requiring flexible read and write operations.
Innovation Solution
The method involves dividing each unit of flash memory into a data field and an address field, allowing for random access similar to EEPROM. This is achieved by allocating a part of the units as a first page in a sector and using a control method to manage the writing and reading of data, ensuring that only the necessary units are updated.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If conventional flash memory requires erasing entire pages before writing, then the write operation can be performed, but the random access characteristics and write flexibility similar to EEPROM are lost
Solution Approach 1:
The patent divides the flash memory into units with address fields and data fields, allowing individual unit-level operations instead of full-page erasures. Each unit can be independently accessed and written to, enabling random access characteristics similar to EEPROM while maintaining flash memory's structural organization.
Solution Approach 2:
The patent introduces a dynamic addressing mechanism where the address field in each unit can be updated to point to the latest data location. This allows the system to dynamically track and access the most recent data without requiring full-page erasures, providing flexible write operations while maintaining structural integrity.
2Duration of action of stationary object
If flash memory uses traditional page-based erasing, then the memory structure is simple, but the lifespan is reduced due to frequent full-page erasures
Solution Approach 1:
By segmenting the flash memory into addressable units with individual address fields, the patent enables granular write operations that only affect specific units rather than entire pages. This reduces the frequency and impact of erasure operations, directly extending memory lifespan while maintaining write efficiency.
Solution Approach 2:
The patent implements a mechanism where updated data is written to new units and the address field is updated to point to the new location. The old data in the previous location is effectively discarded without requiring full-page erasures, as only the specific unit being updated needs to be rewritten with the new address pointer.
3Reliability
If flash memory writes require full-page erasure, then the write operation can be performed, but the read and write cycle count is limited
Solution Approach 1:
The patent segments the flash memory into independently addressable units, allowing random write operations at the unit level rather than requiring full-page erasures. This segmentation enables multiple read-write cycles on the same logical address without degrading the memory, as each unit can be independently updated without affecting other units.
Solution Approach 2:
The patent pre-establishes address fields in each unit that track the latest data location. This preliminary addressing structure allows the system to directly access and update the correct units without requiring full-page erasures, enabling high-cycle durability while maintaining random write flexibility.
Data Source
AI summary
A method for emulating electrically-erasable programmable read-only memory and a flash memory system are disclosed. The flash memory system includes a control circuit and a flash memory. Each unit of the flash memory is divided into a data field and an address field. A plurality of units are allocated as a first page. When the control circuit receives an instruction to read a specific storage unit of the sector, it determines, starting from an initial unit of an initial page, whether the address field of the unit has been written; when the address field has been written, finding a next address according to the address field until a target unit with an address field that has not been written is found. The control circuit reads the data field of the target unit.