Multi-bit Flash Memory Data Validity via Segmented 1-Bit Storage
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Solution Overview
Problem
Multi-bit flash memory devices face challenges in determining the validity of data during power failures, especially when programming is interrupted, leading to uncertainties in the programmed state of memory cells due to the complex threshold voltage distributions and the difficulty in reprogramming the most significant bit page.
Innovation Solution
The solution involves programming multi-bit flash memory cells using complementary data pairs, where each page includes original data and its inverted data, with error detection codes, to ensure that only meaningful 1-bit data is stored in each cell, reducing uncertainty and allowing for accurate validity determination upon power failure by maintaining a complementary relationship between data pairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-bit memory cells are programmed to store multiple bits of data, then storage capacity is improved, but determining data validity after power failure becomes difficult
Solution Approach 1:
The patent segments the multi-bit data storage into multiple independent 1-bit memory cells, where each cell stores only one bit of data. This segmentation allows for reliable validity determination of each bit independently after power failure, while still achieving multi-bit storage capacity through the combination of multiple cells working together.
2Quantity of substance
If complex threshold voltage distributions are used to increase storage density, then storage capacity is improved, but error detection and data validity becomes more difficult
Solution Approach 1:
By dividing multi-bit data into separate 1-bit storage units, each with its own simple threshold voltage distribution, the patent eliminates the complexity of detecting and measuring errors in multi-level threshold voltage distributions while maintaining high storage density through parallel cell utilization.
Solution Approach 2:
The patent introduces error detection codes as an intermediary mechanism that works alongside the segmented 1-bit storage structure. These codes provide an additional layer of error detection capability that complements the simplified threshold voltage measurements of individual 1-bit cells.
3Productivity
If data is stored in multi-bit memory cells, then storage efficiency is improved, but reprogramming after power failure becomes more difficult
Solution Approach 1:
The patent segments multi-bit data storage across multiple 1-bit memory cells, allowing individual cells to be reprogrammed independently after power failure. This segmentation dramatically simplifies the reprogramming process compared to reprogramming entire multi-bit cells, as only the affected 1-bit cells need to be reprogrammed rather than the complete multi-bit unit.
Data Source
AI summary
Methods of operating a non-volatile multi-bit memory device can include programming multi-bit memory cells included in one page of the device with page data including an error detection code based on the page data and determining the validity of the page data using the error detection code read from the multi-bit memory cells in response to an error during programming of the multi-bit memory cells, wherein the multi-bit memory cells in the one page are configured to store a single bit of the page data.