Flash Memory Select Gate Oxide Barrier for Erase Stability

Solution Overview

Problem

Flash memory units face challenges in controlling electron removal during data erasing, leading to over-erasing and misreading issues due to the formation of a conducting channel region without applied voltage, which existing separated gate structures fail to stabilize effectively.

Innovation Solution

A method involving ion implantation and oxygen ion implantation to form an oxide layer between the floating gate and select gate, preventing N-type ion diffusion and thus maintaining the 'off' state of the channel region under the select gate, enhancing the program and erase margins.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a separated gate structure is formed to prevent over-erasing, then the reliability of flash memory is improved, but the device complexity increases

Engineering Contradiction:

Improveflash memory reliabilityVSAvoidgate structure complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The gate structure is segmented into a control gate and a select gate that are spatially separated and independently controlled. The control gate is positioned over the floating gate for program/erase operations, while the select gate is positioned at the side to control the select transistor, preventing the conducting channel from forming under the select gate during erasing operations.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

An oxide layer is introduced as an intermediary barrier between the floating gate and the select gate. This oxide layer prevents N-type ion diffusion from the floating gate to the select gate, thereby maintaining the select gate's ability to keep the channel region in an 'off' state and preventing misreading.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If ion implantation is performed to form the floating gate, then the data storage capability is improved, but N-type ion diffusion to the select gate causes poly silicon depletion and misreading

Engineering Contradiction:

Improvedata storage capabilityVSAvoidpoly silicon depletion

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

An oxide layer is introduced as an intermediary barrier between the floating gate and the select gate. This oxide layer prevents N-type ion diffusion from the floating gate to the select gate, thereby maintaining the select gate's ability to keep the channel region in an 'off' state and preventing misreading.

Inventive Principle:

Principle #24Intermediary (Mediator)

Solution Approach 2:

The harmful N-type ion diffusion path is extracted or removed from the system by positioning the select gate laterally away from the floating gate and introducing the oxide layer barrier, thereby eliminating the source of poly silicon depletion in the select gate.

Inventive Principle:

Principle #2Taking out (Extraction)

3Reliability

If the channel region is kept in 'off' state under the select gate, then data misreading is prevented, but the manufacturing precision requirements increase

Engineering Contradiction:

Improvedata reading accuracyVSAvoidgate positioning precision

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The gate structure is segmented into a control gate and a select gate that are spatially separated and independently controlled. The control gate is positioned over the floating gate for program/erase operations, while the select gate is positioned at the side to control the select transistor, preventing the conducting channel from forming under the select gate during erasing operations.

Inventive Principle:

Principle #1Segmentation

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the stability and performance of flash memory units by preventing poly silicon depletion in the select gate, reducing data misreading and enhancing writing/reading efficiency.

Implementation Method 1

performing an oxygen ion implantation onto a portion of the first semiconductor layer between the position of a subsequently formed floating gate and a position of a subsequently formed first select gate to form an oxide layer

Methodology Applied

Scientific EffectDiffusion barrier: Diffusion Barrier

Implementation Method 2

performing an ion implantation onto a portion of the first semiconductor layer corresponding to a position of a subsequently formed floating gate

Methodology Applied

Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS9012317B2Flash memory and fabrication method thereof

Publication Date: 2015.04.21 SEMICON MFG INT (BEIJING) CORP

AI summary

A method is provided for forming a flash memory. The method includes providing a semiconductor substrate; and forming a first dielectric layer. The method also includes forming a first semiconductor layer on a surface of the first dielectric layer; and performing an ion implantation onto a portion of the first semiconductor layer corresponding to a position of a subsequently formed floating gate. Further, the method includes performing an oxygen ion implantation process onto a portion of the first semiconductor layer between the position of the subsequently formed floating gate and the position of a subsequently formed first select gate to form an oxide layer; and forming a second dielectric layer having an opening exposing the position of the first select gate. Further, the method also includes forming a second semiconductor layer on the second dielectric layer; and forming a flash cell and a select gate structure.