Flash Memory Select Gate Dielectric Segmentation
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Solution Overview
Problem
Conventional methods for fabricating nonvolatile flash memory cells are limited by the dual use of gate dielectric materials, which restricts the independence of memory cell processing from logic device processing and results in suboptimal select gate dielectric layers.
Innovation Solution
The method involves depositing a tunnel dielectric layer and a floating gate material over a semiconductor substrate, forming control gate stacks, and creating select gate areas with a dedicated select gate dielectric layer, independent of logic area processing, allowing for improved process control and material quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate dielectric material is deposited over both memory and logic areas, then processing optimization is achieved, but memory cell processing independence is limited
Solution Approach 1:
The gate dielectric layer is segmented into two distinct layers: a first gate dielectric layer formed in the logic area and a second gate dielectric layer formed in the memory area. This segmentation allows each layer to be independently optimized for its specific function while maintaining overall processing efficiency.
Solution Approach 2:
Different gate dielectric layers are used in different areas: the logic area receives a gate dielectric layer optimized for logic device performance, while the memory area receives a dedicated gate dielectric layer optimized for memory cell performance. This local quality differentiation resolves the contradiction between processing optimization and processing independence.
2Ease of manufacture
If dual use of gate dielectric is implemented, then manufacturing efficiency is improved, but select gate dielectric layer quality deteriorates
Solution Approach 1:
The gate dielectric structure is divided into separate first and second gate dielectric layers, allowing the second layer in the memory area to be specifically optimized for select gate dielectric quality without compromising manufacturing efficiency in the logic area.
Solution Approach 2:
The second gate dielectric layer is specifically engineered for the memory area with properties optimized for select gate dielectric performance, while the first gate dielectric layer serves the logic area. This local quality differentiation enables high manufacturing precision for the select gate dielectric layer while maintaining overall manufacturing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of integrated circuits with improved select gate dielectric layers and nonvolatile memory devices that are less dependent on logic gate dielectric layers, resulting in enhanced cell parameter uniformity and performance.
Implementation Method 1
depositing a tunnel dielectric layer over a semiconductor substrate
Implementation Method 2
depositing a tunnel dielectric layer over a semiconductor substrate
Implementation Method 3
depositing a floating gate material over the tunnel dielectric layer
Implementation Method 4
depositing a floating gate material over the tunnel dielectric layer
Data Source
AI summary
Methods for fabricating memory cells, methods for fabricating integrated circuits having memory cells, and integrated circuits having memory cells are provided. In one example, a method for fabricating a memory cell includes depositing a first tunnel dielectric layer over a semiconductor substrate. The method includes depositing a floating gate material over the first tunnel dielectric layer. The method forms two control gate stacks over the floating gate material, defines a source line area between the two control gate stacks, and defines select gate areas adjacent the two control gate stacks. The method includes depositing a second tunnel dielectric layer over the select gate areas of the semiconductor substrate. Further, the method includes forming select gates over the second tunnel dielectric layer over the select gate areas of the semiconductor substrate. The second tunnel dielectric layer forms a gate dielectric layer for each select gate.