Flash Memory Select Gate Planarization via Spacer Masking
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Solution Overview
Problem
Conventional flash memory cell manufacturing processes result in non-planar top surfaces of select gates, leading to unstable contact plug landing and increased resistance, which affects the performance of the flash memory cell.
Innovation Solution
A method is developed to form a select gate with a planar top surface using a spacer as a mask, where the spacer is self-aligned and used to define the location of the select gate, thereby simplifying the manufacturing process and avoiding mask shift issues, which improves the consistency of the select gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a blanket etching process is performed to form select gates using the gate stack layer as a stop layer, then the select gates can be formed at two sides of the gate stack layer, but the top surface of the select gate becomes non-planar, causing unstable contact plug landing and increased resistance
Solution Approach 1:
A planarization layer is formed over the select gate before subsequent processing steps. This preliminary action ensures that the contact plug will land on a planar surface, resolving the issue of unstable contact plug landing and high resistance caused by the non-planar select gate top surface.
Solution Approach 2:
The planarization layer acts as an intermediary between the non-planar select gate and the contact plug. It provides a planar interface for contact plug formation while maintaining the underlying select gate structure, thereby achieving both ease of manufacture and manufacturing precision.
2Productivity
If a mask is used to cover one side of the gate stack layer and RIE process is performed to remove the select gate at the other side, then the structure of the flash memory cell can be completed, but the non-planar top surface of the spacer-shaped select gate causes unstable contact plug landing
Solution Approach 1:
The planarization layer is formed in advance before contact plug formation. This preliminary action ensures that subsequent contact plug fabrication can proceed with high reliability, eliminating the instability caused by the non-planar select gate surface while maintaining the efficient RIE process.
Solution Approach 2:
The planarization layer serves as a mediator that decouples the select gate formation process from the contact plug formation requirements. It allows the RIE process to proceed efficiently while ensuring reliable contact plug landing on a planar surface.
Data Source
AI summary
A method of fabricating a semiconductor device includes the following steps. At least a first gate stack layer and at least a second gate stack layer protruding from a conductive layer on a substrate are provided. Subsequently, two spacers and a protective layer are formed on the conductive layer, and the two spacers and the protective layer jointly surround the protruded first gate stack layer and the protruded second gate stack layer. The two spacers and the protective layer are used as a mask to remove a part of the conductive layer. Afterwards, the two spacers and the protective layer are removed.