Flash Memory Select Gate Layout for Smaller Access Transistors
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Solution Overview
Problem
Traditional semiconductor manufacturing methods for flash memory cells face challenges in shrinking the minimum gate length of access transistors due to feature differences and the need for thick photoresistors, which limits the shrinking of space between polysilicon layers.
Innovation Solution
A manufacturing method that involves forming a stacked gate with a floating gate and a control gate, followed by the deposition of a select gate conductive layer, and then using an etch-back process without a mask to symmetrically form select gates around access transistors, allowing for easier shrinking of the access transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a mask is used when forming an access transistor to prevent cell leakage, then cell leakage is prevented, but feature differences between left and right cells occur, limiting the ability to shrink the minimum gate length
Solution Approach 1:
The patent removes the mask step from the access transistor formation process. Instead of using a mask to define the access transistor gate, the method forms the stacked gate (floating gate and control gate) first, then uses etch-back to expose the select gate patterns. This extraction of the mask step eliminates the feature differences caused by mask alignment while maintaining cell leakage prevention through the stacked gate structure.
Solution Approach 2:
The patent inverts the traditional formation sequence by first forming the stacked gate structure and then using etch-back to expose the select gate patterns, rather than forming access transistors with masks first and then adding the stacked gate. This inversion allows symmetric formation of select gates and eliminates mask-related feature differences.
2Manufacturing precision
If a thick photo resistor is used for etching floating gate polysilicon, ONO layer, and control gate polysilicon, then etching precision is improved, but the space between polysilicon layers of the floating gate cannot be shrunk
Solution Approach 1:
The patent removes the photo resistor thickening requirement by eliminating the need to etch floating gate polysilicon and control gate polysilicon with photoresist masks. The stacked gate structure is formed first, and select gates are exposed through etch-back without requiring thick photoresist, thereby enabling space reduction between polysilicon layers.
Solution Approach 2:
The patent changes the etching process parameters by using etch-back to expose select gate patterns rather than using photoresist-based etching. This parameter change allows for thinner photoresist or alternative patterning methods, enabling reduced spacing between polysilicon layers while maintaining etching precision through controlled etch-back processes.
3Ease of manufacture
If traditional manufacturing methods are used, then process simplicity is maintained, but the minimum gate length of access transistors cannot be shrunk due to feature differences and thick photo resistor requirements
Solution Approach 1:
The patent extracts and removes the mask step from the traditional manufacturing process. By forming the stacked gate first and using etch-back to expose select gate patterns, the method eliminates mask alignment complexity and thick photoresist requirements, enabling minimum gate length shrinkage while maintaining manufacturing feasibility.
Solution Approach 2:
The patent inverts the traditional process sequence by forming stacked gates before access transistors and using etch-back instead of mask-based patterning. This inversion simplifies the process by removing mask steps while enabling dimension reduction, achieving both ease of manufacture and scalability to smaller dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables the symmetric formation of select gates, facilitating the shrinking of access transistors and improving electrical performance by ensuring identical electrical characteristics across transistors.
Implementation Method 1
forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate
Implementation Method 2
forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate
Data Source
AI summary
A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate