Flash Memory Erase Verification Selective Sector Assignment

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Solution Overview

Problem

Conventional erase verification methods in serial flash memory waste time by performing erase verification on all de-selected sectors repeatedly, even if only some sectors suffer from Pwell disturbance, due to shared Pwell voltage bias during erasing operations.

Innovation Solution

Implement an erase verification method where the flash memory controller selectively assigns only affected de-selected sectors to perform erase verification and program verification, reducing the number of sectors undergoing verification after a predetermined number of erasing operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If erase verification is performed on all de-selected sectors repeatedly, then reliability of erase operation is improved, but time consumption increases

Engineering Contradiction:

Improvereliability of erase operationVSAvoidtime consumption

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies local quality by differentiating the treatment of de-selected sectors based on their specific characteristics. Instead of uniformly verifying all de-selected sectors, the system identifies and verifies only those sectors that are actually affected by Pwell disturbance (those with threshold voltage lower than expected). This selective approach maintains reliability for affected sectors while reducing time consumption for sectors that are not affected.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent utilizes parameter changes by monitoring the threshold voltage parameter of flash memory cells to determine which de-selected sectors require verification. By changing the verification criterion from a fixed universal rule to a dynamic parameter-based selection (threshold voltage < predetermined value), the system adapts the verification scope to actual sector conditions, resolving the contradiction between reliability and time consumption.

Inventive Principle:

Principle #35Parameter changes

2Measurement precision

If all de-selected sectors undergo erase verification, then completeness of verification is improved, but processing efficiency deteriorates

Engineering Contradiction:

Improvecompleteness of verificationVSAvoidprocessing efficiency

Core Design Contradiction:

Measurement precisionVSProductivity

Solution Approach 1:

The patent implements local quality by applying different verification strategies to different sectors based on their individual states. De-selected sectors are categorized into two groups: those affected by Pwell disturbance (requiring verification) and those not affected (skipping verification). This localized approach maintains verification completeness for affected sectors while significantly improving processing efficiency by excluding unaffected sectors from the verification process.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The patent applies partial action by performing erase verification only on the subset of de-selected sectors that are actually affected by Pwell disturbance, rather than unnecessarily verifying all de-selected sectors. The condition (threshold voltage < predetermined value) acts as a filter that selects only the necessary sectors for verification, eliminating excessive verification actions and improving overall processing efficiency.

Inventive Principle:

Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach significantly reduces the time required for erase verification by targeting only sectors with Pwell disturbance, optimizing the erase verification process and minimizing unnecessary operations.

Implementation Method 1

measuring current during ERSV. If current from the cell can be measured, it means the threshold voltage of the cell is lower than 3V

Methodology Applied

Scientific EffectElectrical conduction: Conduction (electrical)

Implementation Method 2

the Pwell is biased a specific voltage about 7V, so that the selected sectors and the de-selected sectors both have the same bias voltage. Due to the same bias voltage on the Pwell during ERS, the electrons existing in the de-selected sectors may also be gradually lost

Methodology Applied

Scientific EffectElectron emission: Electron Beam

Data Source

PatentUS8045374B2Erase verification method of flash memory by selectively assigning deselected sectors

Publication Date: 2011.10.25 ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC

AI summary

A suitable erase verification (ERSV) method of a flash memory apparatus is provided, which is different from the conventional ERSV method. That is, by managing the ERSV operation on the flash memory after at least once of erase operation, a flash memory controller in the flash memory apparatus selectively assigns at least one of de-selected sectors instead of all of the de-selected sectors to perform the ERSV. Therefore, by managing the ERSV operation on the flash memory, the time for the ERSV operation thereon is reduced.