Flash Memory Selective Refresh via Voltage-Based Indicator Comparison
Solution Overview
Problem
Flash memory devices face inefficiencies in the refresh operation of memory blocks, particularly due to the need to refresh all non-erased sectors during an erase cycle, which prolongs the process and can induce data errors and drain stress disturbances.
Innovation Solution
A method that pre-stores indicators for each sector or refresh unit based on a reference voltage level, allowing for selective refresh operations by comparing indicators generated at different voltage levels, thereby identifying and refreshing only necessary sectors or units during an erase cycle.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all non-erased sectors are refreshed during an erase cycle, then data integrity is maintained, but the refresh operation time is prolonged and stress disturbances increase
Solution Approach 1:
The patent segments the memory block into multiple refresh units, each with its own indicator stored in the storage unit. Instead of treating the entire memory block as a single unit requiring uniform refresh, the system divides it into manageable segments (refresh units) that can be independently evaluated and refreshed based on their specific needs, thereby reducing overall refresh time while maintaining data integrity.
Solution Approach 2:
The patent implements partial refresh action by selectively refreshing only those refresh units whose indicators indicate data errors, rather than refreshing all non-erased sectors. The control unit compares stored indicators with newly generated indicators and performs refresh operations only on the necessary portions, avoiding unnecessary refresh operations on already healthy data.
2Reliability
If all non-erased sectors are refreshed during an erase cycle, then data integrity is maintained, but the number of refresh operations increases causing more stress disturbances
Solution Approach 1:
By segmenting the memory block into multiple refresh units with individual indicators, the patent enables targeted refresh operations on specific segments rather than applying stress uniformly across all non-erased sectors. This segmentation allows the system to identify and refresh only the problematic segments, minimizing stress disturbances to healthy areas.
Solution Approach 2:
The patent converts the potential harm of stress disturbances into a benefit by using the indicator comparison mechanism. The indicators serve as early warning signals that allow the system to perform refresh operations only when and where needed, transforming what would be a harmful blanket refresh approach into a beneficial targeted approach that actually reduces overall stress disturbances.
3Productivity
If indicators are pre-stored for each refresh unit, then selective refresh operations can be performed, but the device complexity increases
Solution Approach 1:
The patent segments the storage unit into multiple indicator storage locations, each corresponding to a specific refresh unit. This segmentation organizes the complexity into manageable, structured units rather than a monolithic complex system. Each indicator is independently stored and managed, making the overall system more organized and easier to control despite the increased number of components.
Solution Approach 2:
The storage unit is designed with a universal structure that can store indicators for multiple refresh units using the same format and access methodology. This multi-functional design allows the same storage mechanism to serve multiple purposes (storing indicators for different refresh units), thereby managing complexity through standardization rather than requiring unique storage solutions for each refresh unit.
Data Source
AI summary
A memory device includes a memory block including a plurality of sectors, and a control unit configured to: pre-store a plurality of first indicators in a storage unit, the plurality of first indicators respectively corresponding to a plurality of refresh units in the memory block, each refresh unit including at least one sector, and the first indicators being generated based on a first reference voltage level; and in an erase cycle for erasing a target sector of the memory block: read data from a selected one of the refresh units with a second reference voltage level; generate a second indicator for the selected refresh unit based on the data; compare one of the first indicators corresponding to the selected refresh unit with the second indicator of the selected refresh unit; and if the second indicator is not equal to the first indicator, refresh data in the selected refresh unit.