Flash Memory Floating Gate Self-Aligned Formation
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Solution Overview
Problem
The challenge in fabricating flash memory devices is the difficulty in reducing device dimensions and increasing integration due to the complexity of photolithographic processes for defining floating and control gates, which limits the gate-coupling ratio and increases production costs.
Innovation Solution
A self-aligned process is used to form floating and select gates, eliminating the need for photolithographic techniques in forming control gates and increasing the gate-coupling ratio by forming right-angled triangular-shaped floating gates with tilted surfaces, thereby enhancing the overlapping area with control gates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithographic and etching processes are used to define floating gate and control gate, then the gates can be formed with standard processes, but the processing difficulty increases and the critical dimension limitation prevents further reduction of line width
Solution Approach 1:
The patent employs a self-aligned process where the floating gate is formed first, then used as an alignment reference for forming the control gate. This self-service approach eliminates the need for separate photolithographic patterning steps, automatically achieving precise alignment without increasing processing complexity
Solution Approach 2:
The patent replaces the photolithographic mechanical system with a chemical vapor deposition-based self-aligned formation process. Instead of using light exposure and photoresist patterns, the control gate is formed by depositing conductive material conformally over the floating gate and performing selective etching, substituting optical-mechanical processes with chemical-physical processes
2Reliability
If the overlapping area between control gate layer and floating gate is increased to increase capacitance, then the gate-coupling ratio improves, but the device dimension reduction becomes more difficult
Solution Approach 1:
The patent utilizes vertical stacking in the third dimension by forming the control gate directly over the floating gate in a stacked configuration. This vertical arrangement increases the overlapping area and capacitance without expanding the lateral footprint, allowing device dimension reduction while maintaining or improving gate-coupling ratio
Solution Approach 2:
The patent employs a stacked gate structure combining floating gate material (e.g., polysilicon) and control gate material (e.g., doped polysilicon or metal) in a vertical composite configuration. This composite structure maximizes the overlapping area between gates while maintaining compact lateral dimensions, achieving high gate-coupling ratio in a miniaturized device
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the manufacturing process, reduces production costs, increases the gate-coupling ratio, improves device performance, and allows for higher integration density, resulting in faster operating speeds and improved data storage capabilities.
Implementation Method 1
a thermal oxidation process is performed to form an oxide layer over the exposed first conductive layer
Data Source
AI summary
A method for manufacturing flash memory is provided. A tunneling dielectric layer, a conductive layer and a patterned mask layer that exposes a portion of the conductive layer are formed on a substrate. An oxide layer is formed on the exposed conductive layer so that the conductive layer is partitioned through the oxide layer into blocks. The oxide layer is removed and an inter-gate dielectric layer is formed in the opening. A control gate that completely fills the opening is formed. A cap layer is formed over the control gate. The mask layer is then removed. Using the cap layer as a mask, a portion of the conductive layer is removed to form two floating gates under the control gate. An insulating layer is formed on the substrate. Source/drain regions are formed in the substrate on the respective sides of the control gate.