Flash Memory Bandwidth via Sensing Circuitry Extraction
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Solution Overview
Problem
Conventional NAND flash memory devices face limitations in input/output bandwidth due to the dominance of wordline/bitline driver circuits, which restrict the number of planes that can be supported and thus limit the overall bandwidth, making it challenging to meet increasing application requirements without significant changes to the cell design.
Innovation Solution
The solution involves separating the sensing circuitry from the logic circuitry and placing it on a separate die, allowing for parallel access to multiple flash memory cell planes, and using 3D wafer bonding or through silicon vias for connection, thereby increasing the area available for sensing circuits and improving bandwidth without altering the existing cell structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If wordline/bitline driver circuits are used in conventional NAND flash memory, then the device structure is simple and manufacturing is easier, but the input/output bandwidth is limited and the number of supported planes is restricted
Solution Approach 1:
The device is divided into multiple independent planes, with each plane having its own sensing circuitry and bitline circuits. This segmentation allows parallel access to multiple planes simultaneously, thereby increasing overall I/O bandwidth without requiring complete redesign of the entire device structure
Solution Approach 2:
The patent transitions from a two-dimensional planar architecture to a three-dimensional stacked architecture by placing multiple planes vertically one on top of another. This dimensional change enables more planes to be packed into the same footprint area, increasing bandwidth while maintaining a compact form factor
2Productivity
If the number of planes is increased to improve bandwidth, then I/O speed increases, but the area required for wordline/bitline drivers increases
Solution Approach 1:
The sensing circuitry is extracted from the conventional integrated structure and placed in a separate dedicated sensing block. This extraction removes the sensing functions from the wordline/bitline driver area, allowing the driver circuits to remain compact while the sensing circuits can be expanded independently to support more planes
Solution Approach 2:
Multiple planes are stacked vertically in the third dimension rather than being arranged horizontally. This vertical stacking allows more planes to be accommodated within the same die area, increasing I/O speed without proportionally increasing the lateral area required for driver circuits
3Area of stationary object
If sensing circuitry is integrated with logic circuitry in the same die, then device complexity is reduced, but the area available for sensing circuits is limited
Solution Approach 1:
The device is segmented into two separate functional blocks: a logic circuitry block and a sensing circuitry block. The sensing block is dedicated exclusively to sensing operations and can be independently optimized for area and performance, while supporting multiple planes through parallel sensing capabilities
Solution Approach 2:
Through-silicon vias (TSVs) are introduced as intermediary connection structures to bridge the sensing circuitry block and the bitline circuits. These TSVs enable vertical signal transmission between different die layers, allowing the sensing circuits to access multiple planes without being physically integrated with the logic circuitry
Data Source
AI summary
A flash memory device includes a plurality of flash memory cell arrays, wherein: a flash memory cell array in the plurality of flash memory cell arrays comprises a plurality of layers of flash memory cell planes; and a flash memory cell plane includes a plurality of flash memory cells. The flash memory device further includes a logic circuitry coupled to the plurality of flash memory cell arrays, configured to perform operations using the plurality of flash memory cell arrays; and a sensing circuitry configured to access a corresponding flash memory cell plane among the plurality of flash memory cell planes.