Flash Memory Sensing Node Voltage Control for Off Cell Margin
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Solution Overview
Problem
Flash memory devices face a significant challenge due to low loading capacitance of the sensing node, resulting in substantial voltage decrease and a small off cell margin, which affects data sensing accuracy.
Innovation Solution
A flash memory device with a sensing node voltage controller and page buffer unit that generates precharge and sensing node voltage control signals, precharges the sensing node to a higher voltage than the power supply voltage, and controls the sensing node voltage to increase the off cell margin during data sensing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the sensing node has low loading capacitance, then the sensing node responds quickly to voltage changes, but the voltage decrease due to off cell leakage becomes significant, reducing the off cell margin
Solution Approach 1:
The sensing node is precharged to a voltage higher than the power supply voltage (VDD) before the read operation begins. This preliminary action creates a voltage buffer that compensates for the voltage drop caused by off cell leakage during the sensing period, thereby maintaining sufficient off cell margin while preserving fast response characteristics
Solution Approach 2:
The patent changes the voltage parameter of the sensing node from the conventional VDD level to a higher voltage level (VPrecharge > VDD). This parameter change increases the voltage headroom available to counteract leakage effects, directly improving the off cell margin without sacrificing the low capacitance advantage
2Measurement precision
If the sensing node voltage is increased to improve off cell margin, then data sensing accuracy improves, but the risk of incorrect sensing due to leakage increases without proper control
Solution Approach 1:
The sensing node is precharged to a elevated voltage level before the read operation. This preliminary voltage boost creates a larger voltage margin that can absorb the effects of off cell leakage during the sensing period, thereby improving measurement precision while controlling the harmful leakage effects through proper timing and voltage level selection
Solution Approach 2:
The patent employs a controlled charging mechanism where the sensing node voltage is regulated through a precharge transistor that responds to control signals. This feedback-controlled approach ensures the voltage reaches the optimal level for accurate sensing while preventing excessive voltage that could amplify leakage effects
Data Source
AI summary
A flash memory device wherein off cell margin is increased by controlling a voltage of a sensing node and a corresponding reading method, wherein the flash memory device includes a memory cell array; a sensing node voltage controller generating a precharge voltage and a sensing node voltage control signal; and a page buffer unit connected to the memory cell array through bit lines and having page buffers. The page buffers include a bit line connection unit connected between a corresponding bit line and a sensing node, that controls a voltage of the sensing node according to the sensing node voltage control signal; a precharge unit which precharges the sensing node according to the precharge voltage responsive to a precharge control signal; and a data input/output unit sensing a voltage level of the sensing node responsive to a latch control signal and outputting the data of the selected memory cell.