Flash Memory Cell Structure With Separate Program and Erase Paths

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Solution Overview

Problem

Traditional flash memory cells face reliability issues due to excessive stress on the tunnel oxide from using the same electron path for both programming and erasing, leading to low endurance cycles.

Innovation Solution

The flash memory cell employs separate electron paths for programming and erasing by optimizing the source and drain areas, using a heavily doped tunnel implant to define these regions, and employing an asymmetric structure to minimize stress on the tunnel oxide.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If the same electron path is used for both programming and erasing, then the device structure is simple, but the tunnel oxide experiences excessive stress leading to low reliability

Engineering Contradiction:

Improveelectron path structureVSAvoidtunnel oxide stress resistance

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent divides the single electron path into two separate paths: one for programming (source to floating gate) and one for erasing (floating gate to drain). This segmentation allows independent optimization of each path, reducing stress on the tunnel oxide and improving reliability while maintaining structural simplicity through symmetric design.

Inventive Principle:

Principle #1Segmentation

2Ease of manufacture

If the same portion of tunnel oxide is used for both program and erase, then the manufacturing process is simple, but the endurance cycles are limited to 1K

Engineering Contradiction:

Improvetunnel oxide formation processVSAvoidendurance cycles

Core Design Contradiction:

Ease of manufactureVSDuration of action of moving object

Solution Approach 1:

The tunnel oxide is functionally segmented into two distinct regions: a source tunnel oxide for programming and a drain tunnel oxide for erasing. Although formed in the same manufacturing process, the separate functional regions allow independent wear management, enabling endurance cycles to increase from 1K to 160K-170K by preventing cumulative damage in a single oxide region.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent applies different doping concentrations and geometric dimensions to the source and drain regions. The heavily doped tunnel implant creates localized high-quality tunneling regions with optimized properties for their specific functions, allowing the source and drain tunnel oxides to have different characteristics optimized for their respective program and erase operations.

Inventive Principle:

Principle #3Local quality

3Reliability

If separate electron paths are implemented with optimized source and drain areas, then the tunnel oxide stress is reduced, but the device structure becomes more complex

Engineering Contradiction:

Improvetunnel oxide stress resistanceVSAvoidsource drain structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The patent employs asymmetric source and drain structures with different doping concentrations and geometric dimensions. The source and drain are optimized independently for their specific functions, creating an asymmetric design that reduces tunnel oxide stress. This asymmetry is balanced by the overall symmetric layout of the flash memory cell, maintaining manufacturability while achieving stress reduction.

Inventive Principle:

Principle #4Asymmetry

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design significantly increases the endurance of the flash memory cell to 160K-170K cycles, compared to conventional cells achieving only 1K cycles, by reducing oxide trapping density and optimizing tunneling efficiency.

Implementation Method 1

a negative bias on the control gate and a positive voltage on the p-type is required for Fowler-Nordheim tunneling, which is a process of moving electrons from the control gate into the floating gate

Methodology Applied

Scientific EffectFowler-Nordheim tunneling:

Implementation Method 2

traditional flash memory cells program using hot carrier injection and substrate tunnel erase

Methodology Applied

Scientific EffectHot carrier injection:

Data Source

PatentUS12484258B2Flash memory cell structure having separate program and erase electron paths

Publication Date: 2025.11.25 ALLEGRO MICROSYSTEMS LLC

AI summary

In one aspect, a flash memory cell includes a well having a first-type dopant, a source having a second-type dopant and formed within the well, a drain having the second-type dopant and formed within the well, a floating gate above the well, a control gate above the floating gate, an oxide compound disposed between the floating gate and the control gate, and a tunnel oxide disposed between the floating gate and the well. The flash memory cell is configured, in one of a program mode or an erase mode, to move an electron from the source to the floating gate. The flash memory cell is configured, in the other one of the program or the erase mode, to move an electron is from the floating gate to the drain.