Flash Memory Cell With Separate Wordline And Erase Gates
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Solution Overview
Problem
Scaling down non-volatile memory cells is challenging due to low memory cell current and increased array leakage, and reducing tunnel oxide thickness can cause data retention failures in existing split-gate memory cell configurations.
Innovation Solution
A method is developed to form non-volatile memory cells with a floating gate having a sharp edge, a tunnel oxide layer around the edge, an erase gate with a notch facing the edge, and a word line gate formed after the tunnel and erase gates, using the same conductive material for memory and logic device gates, and incorporating high k metal gates for higher current drives, which reduces the number of masking steps and eliminates the coupling gate over the floating gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a single gate structure is used for both wordline and erase functions, then device complexity is reduced, but programming and erase operations cannot be performed simultaneously
Solution Approach 1:
The gate structure is divided into two separate gates: a first gate (wordline) and a second gate (erase gate). This segmentation allows independent control of programming and erase operations, enabling simultaneous execution of both operations without interference, thus resolving the contradiction between operational versatility and structural simplicity.
Solution Approach 2:
The erase function is extracted from the wordline gate and assigned to a dedicated second gate. This extraction enables the wordline gate to focus solely on programming operations while the second gate handles erase operations, allowing simultaneous operation and improving functional adaptability.
2Productivity
If trench isolation is used to define active areas, then device integration is improved, but stress on suspended gates increases due to trench depth
Solution Approach 1:
The isolation structure is designed with different depths in different regions: deeper trenches in areas where stress compensation is needed and shallower trenches where gate stress would be excessive. This local variation in isolation depth allows high device integration while protecting gate structural integrity in critical areas.
Solution Approach 2:
The isolation trenches are designed with asymmetric depths relative to the gate structures, creating a non-uniform isolation landscape that compensates for gate stress in specific locations while maintaining overall high integration density. The asymmetric design allows optimization of both integration and structural strength.
3Quantity of substance
If gate lengths are reduced to increase memory density, then storage capacity is improved, but control over charge transfer becomes insufficient
Solution Approach 1:
A tunnel barrier layer is introduced as an intermediary between the charge storage node and the channel. This tunnel barrier provides precise control over charge transfer even when gate lengths are reduced, enabling high storage density while maintaining accurate charge control through its controlled breakdown characteristics.
Solution Approach 2:
The tunnel barrier layer's thickness and material composition are precisely controlled to change its electrical parameters, allowing it to provide adequate charge transfer control at reduced gate lengths. By adjusting the tunnel barrier parameters, the system maintains manufacturing precision despite smaller feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases memory cell current with thinner gate oxide and shorter gate length, enhances compatibility with low profile logic devices, and improves data retention by protecting the tunnel oxide, while reducing the complexity of the manufacturing process.
Implementation Method 1
a charge storage node comprising a nitride layer
Implementation Method 2
a control gate positioned over the channel and the charge storage node, the control gate controlling transfer of charge between the channel and the charge storage node
Implementation Method 3
a tunnel oxide layer positioned between the channel and the charge storage node
Data Source
Figure 1A~1C
Figure 2A~2C
Figure 3A~3C
AI summary
A method of forming a non- volatile memory cell includes forming spaced apart first and second regions in a substrate, defining a channel region there between. A floating gate is formed over a first portion of the channel region and over a portion of the first region, wherein the floating gate includes a sharp edge disposed over the first region. A tunnel oxide layer is formed around the sharp edge. An erase gate is formed over the first region, wherein the erase gate includes a notch facing the sharp edge, and wherein the notch is insulated from the sharp edge by the tunnel oxide layer. A word line gate is formed over a second portion of the channel region which is adjacent to the second region. The forming of the word line gate is performed after the forming of the tunnel oxide layer and the erase gate.