Flash Memory RAM Management via Set-Level Mapping

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Solution Overview

Problem

Conventional flash memory management methods require significant random access memory (RAM) utilization, leading to high access times and data errors due to limited RAM capacity and the presence of bad blocks in flash memory, especially when the number of bad blocks exceeds a threshold, causing data-storing issues and file system damage.

Innovation Solution

A management method that constructs a mapping table using a hash function, logical set table, physical memory set table, and set status table to reduce RAM utilization by operating at a set level, allowing for efficient data access and storage across physical and logical blocks, thereby minimizing RAM requirements and maintaining data integrity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If the mapping table is stored in RAM to enable fast access, then access speed is improved, but RAM capacity requirements increase beyond available resources

Engineering Contradiction:
Improveaccess speedVSAvoidRAM capacity
Core Design Contradiction:
SpeedVSQuantity of substance

Solution Approach 1:

The mapping table is divided into multiple regions, each corresponding to a specific range of physical memory addresses. Only the region relevant to the current access request is loaded into RAM, reducing memory usage while maintaining fast access for active data ranges.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The mapping table regions are pre-divided into manageable segments before runtime. When an access request arrives, the system proactively loads only the required region into RAM in advance, avoiding full table loading while ensuring fast access to needed data.

Inventive Principle:
Principle #10Preliminary action

2Quantity of substance

If on-demand fetching is used to reduce RAM usage, then RAM capacity requirements decrease, but access response time increases due to construction time

Engineering Contradiction:
ImproveRAM capacityVSAvoidaccess response time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The mapping table is segmented into regions that can be independently loaded. This allows the system to fetch only the necessary region rather than constructing or loading the entire table, reducing both RAM usage and fetch time simultaneously.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The mapping table is pre-divided into regions during system initialization. When access is needed, the corresponding pre-defined region is already ready for quick loading, eliminating the need to construct the table structure at access time and reducing response delay.

Inventive Principle:
Principle #10Preliminary action

3Quantity of substance

If the mapping table is divided into regions to reduce RAM usage, then RAM capacity requirements decrease, but system complexity increases due to region management

Engineering Contradiction:
ImproveRAM capacityVSAvoidmapping table management complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The mapping table is segmented into regions that naturally correspond to physical memory address ranges. This segmentation aligns with the underlying memory structure, making region management more intuitive and less complex than arbitrary divisions.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The region-based structure serves multiple functions: it reduces RAM usage by loading only necessary portions, maintains fast access through targeted region loading, and simplifies bad block management by containing issues within specific regions. This multi-functionality offsets the apparent complexity increase.

Inventive Principle:
Principle #6Universality (Multi-functionality)

4Ease of operation

If conventional management methods are used, then data access is straightforward, but data errors occur when bad blocks exceed threshold causing file system damage

Engineering Contradiction:
Improvedata access simplicityVSAvoiddata integrity
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The mapping table is divided into regions that can be independently managed and validated. This segmentation allows the system to isolate bad blocks within specific regions without affecting the entire mapping table, maintaining data integrity even when bad blocks exceed thresholds.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The presence of bad blocks is converted from a harmful factor into a manageable condition. By using region-based management with hash functions, bad blocks are identified and isolated within specific regions, preventing them from corrupting the entire file system while maintaining overall system reliability.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS8392690B2Management method for reducing utilization rate of random access memory (RAM) used in flash memory
Publication Date: 2013.03.05 GENESYS LOGIC INC
  • US8392690B2 patent drawing
  • US8392690B2 patent drawing
  • US8392690B2 patent drawing

AI summary

A management method for reducing the utilization rate of random access memory (RAM) while reading data from or writing data to the flash memory is disclosed. A physical memory set is constructed from a plurality of physical memory blocks in the flash memory. A logical set is constructed from a plurality of logical blocks wherein the data stored in the logical set are stored in the physical memory set. Further, the data stored in each of the logical blocks are stored in one number of physical memory blocks. A mapping table is constructed and includes a hash function, a logical set table, a physical memory set table, and a set status table for managing the relationship among the physical memory sets, physical memory blocks, and logical blocks while reading data from or writing data to the flash memory. Further, the management method operates and maintains the physical memory sets, the physical memory blocks, and the logical blocks at a set level so that the utilization rate of random access memory is reduced to decrease the access capacity of the random access memory while operating the physical memory blocks and the logical blocks of the flash memory.