Flash Memory Array with Shared Bitlines and Independent Erasure
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Solution Overview
Problem
Flash memory devices require bulk erasure of all cells, making selective erasing of groups cumbersome and inefficient, and separate arrays with additional circuitry increase integrated circuit area, outweighing benefits of independent erasure.
Innovation Solution
A flash memory array with shared bitlines and separate word lines, where row driver circuits allow independent erasure of subarrays by driving one subarray's word lines to a voltage and the other to a high-impedance state, enabling selective erasure without duplicative circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate flash memory arrays are used to enable independent erasure, then selective erasing capability is improved, but integrated circuit area increases due to duplicative bitline decoder and data path circuitry
Solution Approach 1:
The flash memory array is divided into multiple subarrays that can be independently erased. Each subarray has separate word lines while sharing common bit lines, allowing selective erasure of specific sections without requiring completely separate arrays for each subarray.
Solution Approach 2:
Multiple subarrays share common bit lines and data path circuitry, merging resources that would otherwise need to be duplicated in separate arrays. This reduces the overall circuit area while maintaining the ability to independently erase each subarray through separate row driver circuits.
2Device complexity
If bulk erase operation is used to erase all flash memory cells simultaneously, then erasure operation is simplified, but selective erasing of groups becomes cumbersome and inefficient
Solution Approach 1:
The flash memory array is segmented into multiple subarrays with separate row driver circuits for each subarray. This allows the erase operation to be applied selectively to specific subarrays by controlling which row drivers are active, combining the simplicity of bulk erase with the efficiency of selective erasing.
Data Source
AI summary
In one embodiment, an integrated circuit includes a flash memory array with at least first and second subarrays, or sectors, of memory cells. The subarrays have a set of shared bitlines and separate sets of word lines. A bitline driver circuit is coupled to the set of shared bitlines, a first row driver circuit is coupled to the set of word lines of the first subarray, and a second row driver circuit is coupled to the set of word lines of the second subarray. The first and second row driver circuits are operable to enable the memory cells of the first subarray to be erased independently of the memory cells of the second subarray. The two row driver circuits are further operable to enable the memory cells of the second subarray to be erased independently of the memory cells of the first subarray.