Flash Memory Circuit Shared Control Lines
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Solution Overview
Problem
Conventional flash memory devices face limitations in increasing memory density due to structural constraints, particularly in gate-split flash memories, which require additional word lines increasing chip area and complicating manufacturing processes.
Innovation Solution
A memory circuit design that shares control lines between memory units, reducing the chip area occupied and allowing for increased memory density without altering the structure of memory units, by connecting neighboring control lines and using sector decoding units to control voltages efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If gate-split flash memory structures are used to improve programming and erasing performance, then programming efficiency and reliability are improved, but chip area increases due to additional word lines
Solution Approach 1:
The patent merges the functions of multiple first control lines and multiple second control lines into single shared control lines. Specifically, multiple first control lines are connected together to form a shared first control line, and multiple second control lines are connected together to form a shared second control line. This merging reduces the total number of control lines required, thereby decreasing chip area while maintaining the gate-split flash memory structure's programming and erasing performance.
2Quantity of substance
If two silicon nitride layers are used in each bit unit to store 4 bits of data, then memory density is greatly increased, but manufacturing process complexity increases
Solution Approach 1:
The patent implements multi-functionality in the control lines where a single shared first control line serves multiple bit units simultaneously, and a single shared second control line also serves multiple bit units. This universal control approach allows the same control line structure to manage multiple memory cells, achieving high memory density without proportionally increasing manufacturing complexity, as the control line routing and connection schemes follow regular patterns.
3Area of stationary object
If control lines are shared between memory units to reduce chip area, then chip area is reduced, but control voltage management complexity increases
Solution Approach 1:
The patent segments the memory array into multiple sectors, with each sector having dedicated shared first and second control lines. Within each sector, multiple first control lines are connected to form a shared first control line, and multiple second control lines are connected to form a shared second control line. This segmentation approach organizes the control voltage management into manageable sector-level units, reducing the overall complexity compared to a fully integrated control scheme.
Data Source
AI summary
A memory circuit is provided, including: a plurality of sectors, where each sector includes at least two parallel rows of memory units; a first control line, a second control line and a word line corresponding to each row of memory units, where at least two of the first control lines which are in the same sector and neighboring with each other are connected, and at least two of the second control lines which are in the same sector and neighboring with each other are connected; and a plurality of bit lines perpendicular with the word lines. The number of the first and second control lines may be reduced, so decoding units which control the control lines may occupy less chip areas, thereby reducing chip areas occupied by the memory circuit.