Flash Memory Sidewall Protection Against Over-Etching
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Solution Overview
Problem
Conventional flash memory devices suffer from data retention issues due to over-etching during the manufacturing process, which creates charge trap sites on the dielectric pattern, leading to unexpected data erasure and reduced retention characteristics.
Innovation Solution
A method of manufacturing flash memory devices that includes forming an etch-proof layer and a spacer layer on the sidewalls of the conductive stack structures to prevent over-etching and minimize uncovered surfaces of the dielectric pattern, ensuring the dielectric pattern is substantially covered by the floating gate and control gate patterns.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the second etching process is excessively performed to remove the control gate layer and floating gate pattern, then the etching process can be completed thoroughly, but the control gate line and floating gate pattern are over etched, significantly reducing their widths and creating charge trap sites on the dielectric pattern
Solution Approach 1:
An etch-proof layer is formed on the sidewalls of the floating gate pattern and control gate line before the etching process. This preliminary protective action prevents over-etching during the subsequent etching steps, allowing the etching to proceed thoroughly without damaging the gate structures or creating charge trap sites on the dielectric pattern.
Solution Approach 2:
The etch-proof layer acts as an intermediary protective barrier between the etching process and the gate structures. It is specifically positioned on the sidewalls to prevent etchant from attacking the control gate line, floating gate pattern, and dielectric pattern, thereby maintaining their integrity while allowing complete etching of unwanted materials.
2Ease of manufacture
If the etching process is performed to form the stack gate structure, then the control gate line and floating gate pattern can be formed, but the sidewalls of these structures are over etched, reducing their line width and creating uncovered dielectric surfaces
Solution Approach 1:
The etch-proof layer is formed on the sidewalls of the floating gate pattern and control gate line before the etching process that forms the stack gate structure. This preliminary protection ensures that when etching is performed to create the stacked configuration, the sidewalls are not over-etched, maintaining precise line widths and preventing exposed dielectric surfaces.
3Ease of manufacture
If ion implantation is performed to form source and drain regions, then the doping process can be completed, but ions are implanted onto uncovered dielectric pattern surfaces, creating charge trap sites
Solution Approach 1:
The etch-proof layer is formed on the sidewalls before the ion implantation process. This preliminary protective layer prevents ions from being implanted onto the dielectric pattern surfaces, thereby avoiding the creation of charge trap sites that would compromise data retention characteristics.
Solution Approach 2:
The etch-proof layer serves as an intermediary barrier during ion implantation, protecting the dielectric pattern from ion contamination. It prevents ions from reaching and creating charge trap sites on the dielectric surface, while allowing the ion implantation process to proceed for source and drain region formation.
Data Source
AI summary
In a non-volatile memory device and method of manufacturing the same, a device isolation pattern and an active region extend in a first direction on a substrate. A first dielectric pattern is formed on the active region of the substrate. Conductive stack structures are arranged on the first dielectric pattern and a recess is formed between a pair of the adjacent conductive stack structures. A protection layer is formed on a sidewall of the stack structure to protect the sidewall of the stack structure from over-etching along the first direction. The protection layer includes an etch-proof layer having oxide and arranged on a sidewall of the floating gate electrode and a sidewall of the control gate line and a spacer layer covering the sidewall of the conductive stack structures.