Flash Memory Error Correction via SLC to MLC Mode Switching
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Solution Overview
Problem
Flash memory devices, such as NAND Flash, face limitations in error correction, particularly when the number of bit errors exceeds a certain threshold, making it difficult to decode data effectively, especially when operating in SLC mode.
Innovation Solution
The implementation of an error correction method that allows the flash memory to switch between SLC and non-SLC modes, adjusting voltage distribution by writing logic 1 into the most-significant-bit page, enabling the device to operate in MLC or TLC modes to recover data that cannot be decoded in SLC mode, and using a read retry procedure with different voltages to improve data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the flash memory operates in SLC mode with standard decoding procedures, then the device structure is simple and operation is straightforward, but the error correction capability is limited when bit errors exceed a certain threshold
Solution Approach 1:
The patent implements dynamic mode switching between SLC and non-SLC modes based on error detection results. When initial decoding fails, the system transitions from SLC mode to non-SLC mode, adjusting the operating parameters and voltage distribution dynamically to enable successful data recovery that would otherwise be impossible in static SLC mode
Solution Approach 2:
The patent changes the voltage distribution parameters by switching from SLC mode to non-SLC mode. This parameter change allows the most-significant-bit page to be written with logic 1 to adjust voltage distribution, thereby improving the ability to correct errors when standard decoding fails
2Reliability
If the flash memory operates in non-SLC mode with adjusted voltage distribution, then the error correction capability is improved, but the operation complexity and processing time increase
Solution Approach 1:
The patent applies partial action by first attempting standard SLC mode decoding, and only when that fails does it proceed to the more complex non-SLC mode adjustment. This partial application of the complex error correction method minimizes the time penalty while still providing the capability to recover difficult-to-decode data
Solution Approach 2:
The patent performs preliminary error detection after the first read operation to determine whether the data can be recovered by coding. This preliminary assessment allows the system to avoid unnecessary mode switching and voltage adjustment for easily decodable data, thereby reducing overall processing time
Data Source
AI summary
A data reading method, applied to a data storage device that includes a flash memory capable of operating in a SLC mode and a multi-level cell mode. The data reading method includes reading a page corresponding to a first word line of the flash memory in the SLC mode according to a read command of a host to obtain a first data segment, writing a predetermined data into a most-significant-bit page corresponding to the first word line in the multi-level cell mode when the first data segment has an error, and reading the page corresponding to the first word line in the SLC mode again to obtain a second data segment.