Flash Memory Layout Using SLC Parity and MLC Internal Copy
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Solution Overview
Problem
Conventional flash memory systems inefficiently utilize memory space due to the need to dedicate a significant portion for parity check codes, reducing the effective data storage capacity.
Innovation Solution
Implementing an RAID-like error correction code encoding operation that classifies data into groups and generates parity check codes, allowing efficient programming and error correction across single-level-cell and multiple-level-cell blocks, with an internal copy operation to optimize data placement and reduce parity check code requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory controllers program parity check codes into dedicated data pages, then error correction capability is improved, but memory space utilization deteriorates
Solution Approach 1:
The patent merges the functions of data storage and parity check code storage by programming both into the same data pages. The flash memory controller classifies data into multiple groups, programs them into data pages, and then performs XOR operations on these groups to generate parity check codes that are stored in the same memory space, thereby eliminating dedicated parity pages and improving space utilization while maintaining error correction capability
Solution Approach 2:
The patent makes data pages serve multiple functions: they simultaneously store both user data and parity check codes. The same data pages that originally served only for data storage now also function for storing error correction information, achieving multi-functionality and resolving the contradiction between reliability and space utilization
2Reliability
If more parity check codes are programmed into data pages, then error correction capability is improved, but the number of available data pages deteriorates
Solution Approach 1:
The patent combines data and parity check codes in the same data pages through XOR operations on classified data groups. This merging allows the system to generate and store parity information without requiring additional data pages, thereby maintaining the number of available data pages while improving error correction capability
Data Source
AI summary
A flash memory storage management method includes: providing a flash memory module including single-level-cell (SLC) blocks and at least one multiple-level-cell block such as MLC block, TLC block, or QLC block; classifying data to be programmed into groups of data; respectively executing SLC programing and RAID-like error code encoding to generate corresponding parity check codes, to program the groups of data and corresponding parity check codes to the SLC blocks; when completing program of the SLC blocks, performing an internal copy to program the at least one multiple-level-cell block by sequentially reading and writing the groups of data and corresponding parity check codes from the SLC blocks to the multiple-level-cell block according to a storage order of the SLC blocks.