Latent Slow-to-Erase Bit Detection in Flash Memory
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Solution Overview
Problem
Non-volatile memory (NVM) devices face issues with latent slow-to-erase bits, which are difficult to detect and can lead to over-erasure and excessive current leakage, causing performance degradation and eventual failure, as faster bits become over-erased and slow bits prolong erase cycles, leading to inefficient soft programming and potential erase operation failures.
Innovation Solution
A method and apparatus for detecting latent slow-to-erase bits by analyzing the number of erase pulses and maximum soft program pulses across cycles, comparing current and previous pulse counts, and setting thresholds to identify abrupt increases, allowing for early detection and rejection of units with slow-to-erase bits during production testing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the erase cycle duration is extended to ensure all cells are erased, then erase completeness is improved, but faster cells become over-erased causing excessive current leakage
Solution Approach 1:
The patent applies preliminary soft program pulses to faster-to-erase cells before the main erase operation completes. This preliminary action prepares the faster cells by partially programming them during the erase cycle, preventing over-erasure and reducing subsequent current leakage while maintaining complete erasure of all cells in the block
2Manufacturing precision
If soft programming is performed per address with low program bias, then programming precision is improved, but the duration of soft programming increases significantly
Solution Approach 1:
The patent applies soft program pulses selectively only to those addresses that require them based on erase verification results, rather than applying them uniformly to all addresses. This partial action approach maintains the precision benefits of per-address programming while significantly reducing the overall soft programming duration by excluding addresses that are already properly erased
3Productivity
If production testing does not detect latent slow-to-erase bits, then testing time is reduced, but defective units are released causing performance degradation later
Solution Approach 1:
The patent implements a feedback mechanism during production testing that monitors erase cycle characteristics and soft program pulse requirements in real-time. By analyzing variations in erase behavior across multiple cycles and comparing against threshold criteria, the system can identify latent slow-to-erase bits before they cause field failures, maintaining both testing efficiency and device reliability
Data Source
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AI summary
A method (600, 800) and apparatus (100) for detecting a latent slow bit (e.g., a latent slow-to-erase bit) (306) in a non-volatile memory (NVM) (101) is disclosed. A maximum number of soft program pulses among addresses during an erase cycle is counted (602, 815). In accordance with at least one embodiment, a number of erase pulses during the erase cycle is counted (602, 805). In accordance with various embodiments, determinations are made as to whether the maximum number of the soft program pulses has increased at a rate of at least a predetermined minimum rate comparing to a previous erase cycle (604, 812, 819), whether the maximum number of the soft program pulses has exceeded a predetermined threshold (603, 811, 818), whether the number of erase pulses has increased comparing to a previous erase cycle (603, 811, 818), or combinations thereof. In response to such determinations, the NVM is either passed (606, 823) or failed (605,813, 820) on the basis of the absence or presence of a slow bit in the NVM.