Multi-bit Flash Memory Sorting Method Reducing Testing Cycles
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Solution Overview
Problem
Conventional methods for sorting multi-bit per cell flash memory are inefficient and require multiple testing cycles, leading to prolonged sorting times and resource wastage.
Innovation Solution
A method that programs and reads n-bit-per-cell non-volatile memory, where each m-bpc page is subjected to at most one test, allowing for efficient sorting and configuration of blocks into distinct modes based on capacity information, optimizing operation in different bit-per-cell modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional multi-bit per cell flash memory sorting method is used, then all pages are subjected to multiple program/read tests to determine operational mode, but the sorting time increases significantly and testing resources are wasted
Solution Approach 1:
The patent applies preliminary action by first testing pages in the highest bit-per-cell mode (n-bpc) before falling back to lower modes. This sequential approach with early exit determines the operational mode with minimal tests. Specifically, each page is tested once in n-bpc mode, and only if it fails does the system proceed to test in (n-1)-bpc mode, thereby avoiding unnecessary repeated testing and reducing overall sorting time while maintaining accurate mode determination.
2Reliability
If multiple testing cycles are performed for each page, then comprehensive testing is achieved, but the number of testing cycles increases leading to inefficiency
Solution Approach 1:
The patent inverts the conventional testing approach by starting with the highest bit-per-cell mode (n-bpc) and working downward to lower modes, rather than testing from lowest to highest mode. This inversion allows the system to maximize the use of high-capacity modes and only fall back to lower modes when necessary, thereby reducing the total number of testing cycles while maintaining comprehensive testing coverage.
Solution Approach 2:
The patent applies partial action by testing each page only once in n-bpc mode and only proceeding to additional testing in lower modes if the initial test fails. This partial testing approach avoids the excessive action of performing multiple full testing cycles on all pages, thereby improving testing efficiency while still achieving sufficient reliability to determine operational mode.
3Reliability
If low-bit pages are sorted multiple times in conventional method, then thorough sorting is achieved, but resource wastage increases
Solution Approach 1:
The patent applies preliminary action by first attempting to sort pages in the highest bit-per-cell mode before falling back to lower modes. This ensures that pages are tested once in n-bpc mode, and only if they fail does the system proceed to test in lower modes. This approach avoids the resource wastage of performing multiple full testing cycles on all pages, thereby reducing energy consumption while maintaining thorough sorting where needed.
Data Source
AI summary
A method of sorting a multi-bit per cell non-volatile memory includes programming and reading to test an n-bit-per-cell (n-bpc) non-volatile memory, which has a plurality of m-bpc pages, where m is a positive integer from 1 through n. If the m-bpc page fails the test, counting a block associated with the failed m-bpc page to (m-1)-bpc blocks, wherein each said m-bpc page is subjected to at most one time of programming and reading. When m is equal to 1, the 0-bpc block corresponds to a bad block.