Flash Memory Source Line Height and Spacer Configuration
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional NAND-type flash memory devices face challenges in integrating more transistors per unit area due to the height and alignment issues of the source line relative to the gate lines, leading to increased aspect ratios of bitline contact holes and potential short circuits.
Innovation Solution
The design includes a source line with a top surface height equal to or lower than the gate lines, and a configuration where the source line is formed between source spacers, reducing the aspect ratio of the bitline contact hole and minimizing the risk of short circuits by patterning the source line with the selection gate lines and wordlines in a single step.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the source line is formed at a higher level to ensure electrical connection, then electrical reliability is improved, but the aspect ratio of bitline contact holes increases and integration density deteriorates
Solution Approach 1:
The source line is intentionally formed at a lower height level than the gate lines, utilizing the vertical dimension differently. This dimensional repositioning reduces the aspect ratio of contact holes while maintaining electrical connectivity through alternative routing paths via source/drain regions, thereby improving integration density without sacrificing reliability.
Solution Approach 2:
Source/drain regions serve as intermediary elements that provide electrical connection between the lowered source line and the bitline. This mediator approach allows the source line to be positioned at a lower level while still achieving reliable electrical connectivity through the intermediate source/drain regions, resolving the contradiction between height positioning and connection reliability.
2Device complexity
If the source line height is reduced to improve integration density, then manufacturing complexity is reduced, but alignment precision between source line and gate lines becomes more critical
Solution Approach 1:
Source spacers are formed in advance before the source line patterning step. These pre-formed spacers serve as alignment references and protective structures during subsequent etching and deposition processes, making the alignment process more robust and less sensitive to positioning variations, thereby reducing the criticality of alignment precision.
Solution Approach 2:
The source line width is designed to be larger than the gate line width. This parameter change provides a larger target area for alignment, effectively reducing the impact of alignment errors. The wider source line compensates for potential misalignment, making the manufacturing process more tolerant and less complex.
3Ease of operation
If source spacers are used to define source line position, then alignment ease is improved, but the number of manufacturing steps increases
Solution Approach 1:
The source spacers serve multiple functions: they define the position of the source line, act as alignment references for subsequent patterning steps, and provide physical protection to underlying structures. This multi-functionality consolidates several purposes into a single structure, offsetting the additional manufacturing step by eliminating the need for separate alignment markers or protective layers.
Data Source
AI summary
A flash memory device includes a common source region that is disposed in an active region at a side of a ground-selection gate line, being apart from the ground-selection gate line. A pair of source spacers crosses over both top edges of the common source region. A source line fills up a space between the pair of source spacers. The top surface of the source line is equal to or lower than the that of the ground-selection gate line.