Flash Memory Source Line Segmentation for Loading Uniformity

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Solution Overview

Problem

High resistivity of oxide diffusion in flash memory devices leads to uneven source line loadings, impacting memory window and current distribution, particularly in multi-level operations, affecting product performance.

Innovation Solution

The implementation of multiple contact portions and transmit portions coupled to the source line, ensuring consistent resistance paths for bit line signals, thereby minimizing variations in source line loadings and improving memory performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If oxide diffusion is used in flash memory devices, then manufacturing is enabled, but high resistivity causes uneven source line loadings

Engineering Contradiction:

Improvemanufacturing capabilityVSAvoidsource line loading uniformity

Core Design Contradiction:

Ease of manufactureVSManufacturing precision

Solution Approach 1:

The source line is divided into multiple segments with separate contact portions (first contact portion, second contact portion, etc.) instead of a single continuous line. This segmentation allows independent control and optimization of each segment's electrical characteristics, reducing the impact of high resistivity in oxide diffusion and achieving more uniform source line loadings across different bit lines.

Inventive Principle:

Principle #1Segmentation

2Device complexity

If high resistivity oxide diffusion is used, then device structure is simplified, but memory window and current distribution are impacted

Engineering Contradiction:

Improvestructure simplicityVSAvoidmemory window and current distribution

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

Different contact portions are positioned at specific locations along the source line to create localized electrical connections. This local quality approach ensures that each bit line has an optimized connection point, compensating for the high resistivity of oxide diffusion and maintaining consistent voltage levels and current distributions across the memory array without complicating the overall device structure.

Inventive Principle:

Principle #3Local quality

3Manufacturing precision

If multiple contact portions are implemented, then source line loading consistency is improved, but device complexity increases

Engineering Contradiction:

Improvesource line loading consistencyVSAvoidcontact portion configuration

Core Design Contradiction:

Manufacturing precisionVSDevice complexity

Solution Approach 1:

The contact portions are asymmetrically positioned along the source line at strategically selected locations rather than being uniformly distributed. This asymmetric configuration optimizes the electrical characteristics for each region of the memory array, achieving consistent source line loadings while minimizing the total number of contact portions needed and reducing overall device complexity.

Inventive Principle:

Principle #4Asymmetry

Data Source

PatentUS11854625B2Device and method for operating the same

Publication Date: 2023.12.26 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A device is disclosed herein. The device includes at least two transmit portions and at least one contact portion. Each of the at least two transmit portions is configured to receive a bit line signal. The at least one contact portion is couple to the at least two transmit portions respectively and configured to transmit the bit line signals from the least two transmit portions to a source line.