Flash Memory Spacer Gate Structure for Short Channel Effect Reduction
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Solution Overview
Problem
The limitations of photolithography in forming gate structures for flash memory devices restrict cell array integration and lead to serious short channel effects due to narrow line widths, hindering the reduction of unit cell size.
Innovation Solution
A flash memory device is fabricated with a source region, recessed region, floating gates formed on the sidewalls of the recessed region, and control gate electrodes at the sidewalls of the source line, allowing for a spacer structure that enables smaller line widths and increased channel length without photolithography constraints.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If photolithography is used to form gate structures, then manufacturing process is simple, but line width is limited to tens of nanometers causing short channel effects
Solution Approach 1:
The patent replaces the photolithography-based mechanical patterning system with a spacer-based self-aligned deposition system. The gate structure is formed by depositing conformal layers that are then anisotropically etched to create spacers, eliminating the need for photolithographic patterning and enabling sub-10nm line widths without suffering from the resolution limits and short channel effects of conventional photolithography.
2Ease of manufacture
If photolithography is used to form gate structures, then manufacturing process is simple, but cell array integration is restricted by minimum feature size
Solution Approach 1:
The patent replaces photolithography with spacer-based self-aligned deposition, enabling line widths below the photolithographic minimum feature size. This substitution allows for higher cell array integration density by creating narrower gates and smaller unit cell dimensions while maintaining manufacturing feasibility through conformal deposition and anisotropic etching processes.
Solution Approach 2:
The patent transitions from planar photolithographic patterning to three-dimensional spacer formation through conformal deposition. By utilizing the vertical dimension for spacer thickness control and anisotropic etching, the process achieves finer lateral resolution and higher integration density without being constrained by the two-dimensional resolution limits of photolithography.
3Productivity
If narrow line widths are used to reduce unit cell size, then integration increases, but short channel effects become serious
Solution Approach 1:
The patent replaces photolithography with spacer-based self-aligned deposition, enabling precise control of gate line widths at sub-10nm scales. This substitution allows for narrow gates that increase integration density while the self-aligned nature of the process ensures precise dimensional control, preventing the short channel effects that plague conventional narrow-gate devices.
Solution Approach 2:
The patent changes the fundamental parameters of gate formation from photolithographic exposure and development to atomic-layer-deposition thickness control and anisotropic etching. This parameter change enables precise sub-10nm gate width control through atomic-layer precision deposition, allowing narrow gates for high integration while maintaining reliable electrical characteristics by precisely controlling gate dimensions and alignment.
Data Source
AI summary
A flash memory device includes a source region formed in an active region of a semiconductor substrate; a recessed region formed in the active region on either side of the source region, the recessed region including a recess surface having sidewalls; floating gates formed at the sidewalls of the recess surface by interposing a tunnel insulating film; a source line formed on the source region across the active region; and control gate electrodes formed at sidewalls of the source line across a portion of the active region where the floating gates are formed. The floating gates and the control gate electrodes are formed by anisotropically etching a conformal conductive film to have a spacer structure. Cell transistor size can be reduced by forming a deposition gate structure at both sides of the source line, and short channel effects can be minimized by forming the channel between the sidewalls of a recess surface.