Dual Bit Flash Memory Sidewall Spacer Etch Mask
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Solution Overview
Problem
Current flash memory device fabrication techniques limit the ability to scale device dimensions and achieve substantially vertical sidewalls, leading to issues with charge storage node variations and interference in subsequent etching processes.
Innovation Solution
A method involving the formation of sidewall spacers as etch masks to control the length of charge storage nodes and polycrystalline silicon gate structures with substantially vertical sidewalls, allowing for independent design of charge trapping stacks and gate insulators, and the use of impurity dopants to form bitline regions in electrical communication with the nodes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional fabrication techniques are used to scale device dimensions, then device density increases, but charge storage node length variations increase and sidewalls become non-vertical
Solution Approach 1:
The patent introduces sidewall spacers as intermediary structures formed on the charge trapping stack before etching. These spacers act as a mediating element that defines the charge storage node length independently of lithography variations, thereby maintaining manufacturing precision while enabling device scaling and increased density.
2Quantity of substance
If device dimensions are reduced to 45 nm node, then device density increases, but gate insulator isolation becomes necessary and charge trapping stack thickness control becomes difficult
Solution Approach 1:
The patent segments the charge trapping stack into distinct functional regions: a charge storage portion with controlled thickness and a gate insulator portion. This segmentation is achieved through selective etching processes that use sidewall spacers as masks, allowing independent control of each region's dimensions and simplifying the overall fabrication process at scaled dimensions.
3Quantity of substance
If charge storage nodes are made narrower to increase density, then device density increases, but lithography variations have more deleterious effects on node characteristics
Solution Approach 1:
The sidewall spacers serve as intermediary structures that decouple the charge storage node dimension control from the lithography process. By forming spacers with controlled thickness through deposition processes rather than lithography, the patent eliminates the amplification of lithography variations that would otherwise occur in narrower nodes, thereby maintaining precise dimensional control.
4Ease of manufacture
If non-vertical sidewalls are used in charge storage nodes, then fabrication is simpler, but shadowing effects interfere with subsequent etching processes
Solution Approach 1:
The patent performs preliminary action by forming sidewall spacers with substantially vertical sidewalls before the charge storage node etching process. These pre-formed vertical spacers serve as etch masks that prevent shadowing effects during subsequent etching, ensuring uniform node formation without requiring complex in-process adjustments.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables flexible design and scaling of dual bit memory devices, minimizing lithography variations and reducing interference with subsequent etching processes, resulting in consistent charge storage node lengths and improved charge storage characteristics.
Implementation Method 1
Impurity dopants are implanted into the second portion of the substrate to form impurity-doped bitline regions within the substrate
Data Source
AI summary
Methods for fabricating dual bit flash memory devices are provided. Method steps include forming a charge trapping layer overlying a substrate and fabricating two insulating members overlying the charge trapping layer. A polycrystalline silicon layer is provided overlying the charge trapping layer and about sidewalls of the insulating members. Sidewall spacers are formed overlying the polycrystalline silicon layer and about the sidewalls of the insulating members. A portion of the first polycrystalline silicon layer and a first portion of the charge trapping layer are removed. A first insulating layer is conformally deposited overlying the insulating members and the substrate. A gate spacer is formed between the two insulating members and overlying the first insulating layer. The two insulating members are removed and the charge trapping layer is etched to form charge storage nodes. Impurity dopants are implanted into the substrate to form impurity-doped bitline regions within the substrate.