3D Flash Memory Erasing via Staggered Voltage Timing
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Solution Overview
Problem
Conventional semiconductor memory devices face challenges in downscaling due to physical limitations and high costs associated with three-dimensional memory structures, particularly with the MONOS transistor-based collectively patterned memory cells, which suffer from data retention issues due to charge movement between adjacent cells during repeated programming and erasing operations.
Innovation Solution
A nonvolatile semiconductor memory device with a three-dimensionally stacked flash memory configuration that employs a control unit to apply different voltages to electrode portions at varying timing, utilizing a charge storage film, insulating films, and semiconductor pillars to manage the erasing operation by injecting electron holes or removing electrons, thereby reducing electric field stress and improving data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If three-dimensional collectively patterned memory is used to suppress cost increases, then manufacturing cost is reduced, but data retention deteriorates due to charge movement between adjacent cells
Solution Approach 1:
An inter-layer insulating film is introduced between adjacent memory cell groups to prevent charge movement between cells. This intermediary insulating layer acts as a barrier that isolates the electric fields of adjacent cells, thereby maintaining data retention while preserving the cost advantages of collective patterning.
Solution Approach 2:
The insulating film structure is differentiated between cell portions and inter-layer portions. The inter-layer insulating film is specifically positioned at the between-CG regions where charge leakage occurs, providing localized protection without affecting the overall memory structure or requiring changes to the collective patterning process.
2Productivity
If repeated programming and erasing operations are performed, then data can be updated, but load accumulates in the MONOS insulating film between adjacent cells
Solution Approach 1:
The inter-layer insulating film serves as a mediator that prevents electric field coupling between adjacent memory cell groups during programming and erasing operations. By isolating the cells, it prevents load accumulation in the MONOS insulating film even when repeated operations are performed on different cell groups.
Solution Approach 2:
The memory device operates by periodically selecting and programming/erasing specific cell groups while leaving others in standby mode. The inter-layer insulating film ensures that cells not currently being operated on are protected from electric field effects, allowing repeated operations without cumulative damage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively suppresses the accumulation of electric field stress between insulating films and channel layers, enhancing data retention characteristics and reducing costs by optimizing the erasing operation in three-dimensionally stacked memory devices.
Implementation Method 1
The control unit applies a first voltage to a plurality of electrode portions adjacent to each other in one direction at different timing respectively
Implementation Method 2
charge is programmed into a charge trap insulating film
Data Source
AI summary
According to one embodiment, a nonvolatile semiconductor memory device includes a memory unit and a control unit. The memory unit includes a charge storage film, a first insulating film provided adjacent to one surface of the charge storage film, a second insulating film provided adjacent to one other surface of the charge storage film, a semiconductor portion provided adjacent to the first insulating film and a plurality of electrode portions provided adjacent to the second insulating film. The control unit performs a control of applying a first voltage to electrode portions adjacent to each other in one direction at different timing respectively, in an erasing. The erasing is performed by at least one selected from injecting electron holes into the charge storage film and removing electrons from the charge storage film. The first voltage is applied from one of the electrode portions to the charge storage film to be erased.