Flash Memory Standby Circuit Using Capacitor-Held Supply Voltage

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Solution Overview

Problem

Flash memory devices face limitations such as high power consumption and slow operation speed, which affect microprocessor performance and introduce additional latency in communication protocols, particularly in applications requiring fast access times.

Innovation Solution

Implementing a low power standby mode (LP standby mode) that reduces power consumption by shutting down most circuitry, including the voltage regulator, and using an external capacitor to store energy for immediate read operations, allowing fast wake-up times.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If traditional standby mode is used, then power consumption is reduced, but wake-up time is slow and power consumption is not sufficiently reduced

Engineering Contradiction:

Improvepower consumptionVSAvoidwake-up time

Core Design Contradiction:

Use of energy by moving objectVSLoss of time

Solution Approach 1:

The patent applies preliminary action by keeping the voltage regulator and read circuitry in a partially powered state during standby mode, so they are ready for immediate operation. This resolves the contradiction by maintaining fast wake-up capability while still achieving significant power reduction compared to fully active mode.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent segments the power management into different states: fully active mode, standby mode with partial power (voltage regulator on, read circuitry on), and deep power-down mode. This segmentation allows the system to achieve both low power consumption and fast wake-up by using the intermediate standby state.

Inventive Principle:

Principle #1Segmentation

2Use of energy by moving object

If deep power-down mode is used, then power consumption is significantly reduced, but wake-up time becomes slow

Engineering Contradiction:

Improvepower consumptionVSAvoidwake-up speed

Core Design Contradiction:

Use of energy by moving objectVSSpeed

Solution Approach 1:

The patent uses preliminary action by pre-powering the voltage regulator and read circuitry in the standby state, so they are already ready for immediate read operations. This eliminates the slow wake-up time penalty of deep power-down modes while maintaining low power consumption.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements dynamic power management where the system can transition between different power states based on operational needs. The standby mode with partial power provides a dynamic intermediate state that balances power savings with fast wake-up capability.

Inventive Principle:

Principle #15Dynamics

3Use of energy by moving object

If voltage regulator is shut down to reduce power consumption, then power consumption is reduced, but read operations cannot be performed immediately

Engineering Contradiction:

Improvepower consumptionVSAvoidread operation availability

Core Design Contradiction:

Use of energy by moving objectVSProductivity

Solution Approach 1:

The patent applies preliminary action by keeping the voltage regulator and read circuitry powered in the standby state. This ensures that read operations can be performed immediately without waiting for power-up, while still achieving significant power reduction compared to fully active mode.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent uses partial action by powering only the essential components (voltage regulator and read circuitry) in standby mode, not the entire device. This partial power-up achieves both power reduction and immediate read capability.

Inventive Principle:

Principle #16Partial or excessive action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The LP standby mode significantly reduces power consumption to levels comparable to deep power-down modes while maintaining fast wake-up times, addressing the limitations of traditional standby and sleep modes in flash memory devices.

Implementation Method 1

using an external capacitor to store energy for immediate read operations

Methodology Applied

Scientific EffectCapacitance: Capacitance

Data Source

PatentUS12510950B2Low power standby mode for memory devices

Publication Date: 2025.12.30 GLOBALFOUNDRIES US INC

AI summary

A memory device, can include: a control circuit configured to operate the memory device in one of an active mode, a standby mode, and a sleep mode, where the memory device is configured to receive a command from a host device when in the standby mode; a voltage regulator having an output that provides a supply voltage for accessing contents of memory cells in the memory device, where the voltage regulator is off during the sleep mode and the standby mode, and the voltage regulator is on during the active mode; and a storage element configured to maintain the supply voltage to allow the voltage regulator to be turned off during the standby mode, and at least until the voltage regulator turns on in the active mode and supports the supply voltage.