Dynamic Memory State Reassignment for Flash Endurance
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Solution Overview
Problem
Non-volatile memory systems, such as flash memory, face limited endurance due to increased vulnerability and defect levels as cell dimensions shrink, affecting data integrity and requiring more exact programming and reading, which decreases endurance and programming speed.
Innovation Solution
Dynamic reassignment of programming states in memory blocks allows for increased endurance and faster programming by converting memory blocks to operate with fewer states, such as using single level cell (SLC) programming to double the program/erase cycling and increase the total byte written to the system, effectively reducing erase counts and enhancing write performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cell dimensions are shrunk to increase capacity per unit area, then storage density is improved, but cell vulnerability and defect levels increase, worsening data integrity and endurance
Solution Approach 1:
The patent changes the programming state parameters dynamically. Memory blocks are reassigned from multi-state operation (e.g., 8 states for 3 bits per cell) to fewer states (e.g., 2 states for SLC operation) based on detected block conditions. This parameter change allows blocks with higher vulnerability to operate in more robust states, maintaining data integrity while preserving storage capacity.
2Quantity of substance
If more bits per cell are programmed to increase storage capacity, then capacity per unit area is improved, but programming and reading must be more exact, worsening manufacturing precision requirements and endurance
Solution Approach 1:
The patent implements dynamic reassignment of programming states based on block condition detection. Blocks that would require high programming precision for multi-state operation are dynamically converted to operate with fewer states, reducing the precision requirements. This dynamic adaptation allows the system to maintain high capacity where blocks permit while using fewer states where precision would be problematic.
3Quantity of substance
If memory blocks operate with more states to maximize capacity, then storage density is improved, but endurance decreases due to increased vulnerability to program and erase cycling
Solution Approach 1:
The patent dynamically changes the operating state parameter based on block endurance characteristics. Blocks experiencing wear or showing vulnerability to cycling are reassigned from multi-state operation to SLC-like operation with fewer states. This parameter change extends the duration of action (endurance) by reducing stress on vulnerable blocks while maintaining overall storage capacity through selective state assignment.
4Quantity of substance
If programming states are increased to improve storage capacity, then capacity per unit area is improved, but programming speed decreases due to more exact programming requirements
Solution Approach 1:
The patent dynamically adjusts the number of programming states based on block performance characteristics. Blocks that would require slow, precise programming for multi-state operation are converted to operate with fewer states, enabling faster programming. This dynamic reassignment maintains high storage capacity while improving programming speed for blocks where speed is critical.
Data Source
AI summary
A storage device with a memory may include improved endurance and programming speed by modifying the programming states of the memory blocks. For example, the blocks may be three bit memory blocks, but a dynamic reassignment of verify levels and read margins can result in the block acting like a two bit memory block. Memory blocks may be designed for a certain number of bits per cell (i.e. number of states) and the programming is based on that number. However, single level cell (SLC) programming is still possible in addition to programming according to the number of bits per cell that the memory is designed for. Multiple SLC programming steps can be used to modify the number of states for certain memory cells by the memory controller.