Flash Memory Storage Controller Address Error Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory systems face challenges in data protection due to address errors caused by differences in data management units between flash memory modules and hard disk drives, leading to inefficient data updating and potential data loss from concentrated erase cycles and incorrect address translations.
Innovation Solution
A storage system with a memory controller and storage controller that manages data in cache memory, creates protection codes for address identification, and adjusts data lengths to match flash memory specifications, allowing for detection and correction of address errors using RAID groups and error detection/correction codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written in flash memory using traditional address translation without protection codes, then the storage system can operate with simple address mapping, but address errors may occur causing data to be written in wrong physical addresses
Solution Approach 1:
The invention divides the data into multiple segments, each with its own protection code containing address information. This segmentation allows individual address verification without requiring complex system-wide address translation checks, thus improving reliability while managing complexity through modular verification units.
Solution Approach 2:
The protection code acts as an intermediary between the logical address and the physical address. It contains address information that serves as a mediator to verify correctness during write operations, enabling simple address mapping while providing error detection capability through the intermediate protection code layer.
2Productivity
If flash memory blocks are erased every time data in one page is updated, then data can be updated in flash memory, but the data update capacity deteriorates due to the long erase time compared to write time
Solution Approach 1:
The invention performs preliminary actions by maintaining a mapping table that records the correspondence between logical and physical addresses before data updates occur. This allows the system to directly update data in the correct physical location without needing to erase the entire block first, thereby improving update capacity while avoiding time-consuming erase operations.
Solution Approach 2:
The invention changes the parameter of data management from block-based erasure to page-based updates with address translation. By introducing protection codes and mapping tables, the system enables direct page-level writes without full block erasures, transforming the time-consuming erase operation into a faster direct write operation while maintaining data integrity.
3Duration of action of stationary object
If wear-leveling algorithms are implemented to distribute erase cycles, then the lifespan of flash memory is extended, but the device complexity increases due to additional control mechanisms
Solution Approach 1:
The invention makes the mapping table serve multiple functions: it stores address translation information for data access and simultaneously tracks erase cycle counts for wear-leveling. This multi-functionality extends flash memory lifespan through wear-leveling while avoiding the complexity of separate control mechanisms by combining multiple functions into a single data structure.
Solution Approach 2:
The invention merges the address translation function and wear-leveling tracking function into a single mapping table structure. This consolidation allows the system to extend flash memory lifespan through distributed erase cycle management while reducing device complexity by eliminating separate control mechanisms and integrating multiple functions into one unified structure.
4Reliability
If address translation is performed to convert logical addresses to physical addresses in flash memory, then data can be written in correct physical locations, but errors may occur in the conversion process causing data to be written in wrong addresses
Solution Approach 1:
The invention introduces feedback through protection codes that contain address information. After writing data, the system can verify the written address by checking the protection code, providing feedback on address translation accuracy. This simple feedback mechanism improves reliability without requiring complex verification systems by using the protection code itself as the verification signal.
Solution Approach 2:
The invention applies beforehand cushioning by embedding address information in protection codes before data writing occurs. This pre-embedded address verification data acts as a cushion against address translation errors, allowing simple verification during or after the write operation without requiring complex real-time address validation mechanisms.
Data Source
AI summary
To detect an address error in flash memory using a different data management unit from that in a hard disk drive. In cache memory, data read/written from/to a flash memory chip is managed in units of first data lengths. A page, which is the data management unit in a flash memory chip, includes a data section of a second data length from/to which a storage controller can read/write data; and a redundant section. When writing data, the storage controller creates a protection code enabling identification of a write destination page address, divides the data in the cache memory, which is managed in units of first data lengths, into pieces so that the size of each set composed of a piece of the divided write data and its protection code will be of a second data length, and writes the respective sets in a flash memory chip in units of second data lengths.