Flash Memory Storage Layer With Deep Quantum Well
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Solution Overview
Problem
Conventional flash memory cells face challenges in scaling down write/erase voltages while maintaining data retention and preventing charge leakage, particularly due to defects in the tunneling oxide layer and conduction band discontinuity issues with silicon nitride storage layers.
Innovation Solution
A flash memory cell structure incorporating a tunneling layer, a storage layer with a conduction band lower than silicon, and a blocking layer with a high-k dielectric material, along with a gate electrode, to reduce leakage and lower write/erase voltages, using materials like aluminum nitride and high-k dielectric blocking layers to enhance charge retention and reduce electric fields.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the thickness of the tunneling oxide layer is decreased to scale down write/erase voltages, then write/erase voltages are reduced, but charge leakage increases significantly
Solution Approach 1:
The storage layer is segmented into discrete and electrically isolated traps within the wide-bandgap dielectric material, rather than using a continuous conductive layer. This segmentation prevents charge leakage paths that would exist in conventional continuous floating gates, allowing thinner tunneling oxide layers without compromising charge retention.
Solution Approach 2:
The patent changes the bandgap parameter of the storage layer material from conventional silicon nitride to wide-bandgap dielectric materials. This parameter change creates deeper quantum wells that more effectively confine charges, enabling reduced tunneling oxide thickness while maintaining charge retention through the quantum confinement effect.
2Ease of manufacture
If conventional silicon nitride storage layer is used, then manufacturing is simplified, but conduction band discontinuity causes charge leakage
Solution Approach 1:
The patent changes the conduction band parameter by selecting wide-bandgap dielectric materials with conduction bands lower than silicon, creating negative band offsets. This parameter change forms deep quantum wells that provide superior charge confinement compared to conventional silicon nitride, eliminating leakage through conduction band discontinuity.
3Reliability
If thick oxide is used to prevent charge leakage, then data retention is improved, but write/erase voltages increase
Solution Approach 1:
The patent changes the dielectric parameter (bandgap) of the storage layer to wide-bandgap materials. This enables the use of thinner tunneling oxide layers because the wide-bandgap storage layer provides superior charge confinement through deeper quantum wells, compensating for the reduced oxide thickness and maintaining data retention while reducing write/erase voltages.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution achieves reduced leakage, prolonged data retention, and lower write/erase voltages, making the flash memory cells compatible with CMOS logic and suitable for embedded system-on-chip applications with improved write/erase speed and efficiency.
Implementation Method 1
The storage layer preferably has a conduction band lower than a conduction band of silicon... The storage layer comprises a wide-bandgap dielectric material... deeper quantum wells can be formed in the storage layer
Implementation Method 2
The blocking layer is preferably formed of a high-k dielectric material... the blocking layer has a k value of greater than about 3.9
Data Source
AI summary
A flash memory cell includes a substrate and a gate structure formed on the substrate. The gate structure includes a tunneling layer over the substrate, a storage layer over the tunneling layer, a blocking layer over the storage layer, and a gate electrode over the dielectric. The storage layer preferably has a conduction band lower than a conduction band of silicon. The blocking layer is preferably formed of a high-k dielectric material.