Super Flash Memory Channel Stress Transfer for Faster Read Write
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Solution Overview
Problem
The existing 38SF flash memory cells exhibit slow programming and reading speeds due to low electron storage in the floating gate, primarily attributed to suboptimal thickness and uniformity of the floating gate, short transverse electric field maintenance time, and limited electron migration rate, which affects the reading and writing performance.
Innovation Solution
A method involving etching the semiconductor substrate to form a groove alongside the gate structure and applying a stress dielectric layer within this groove, followed by annealing to transfer stress laterally onto the channel region, enhancing carrier mobility and electron storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the floating gate thickness is increased to improve electron storage capacity, then the electron storage capacity improves, but the manufacturing precision and uniformity deteriorate
Solution Approach 1:
The patent applies different stress conditions to different regions of the channel. By forming a stress dielectric layer in grooves at specific locations (source and drain regions), the channel experiences non-uniform stress distribution. This local quality approach allows optimizing electron migration in critical regions without requiring uniform changes across the entire floating gate structure, thus maintaining manufacturing precision while improving electron storage capacity.
2Quantity of substance
If the transverse electric field maintenance time is extended to improve electron migration, then the electron migration rate improves, but the programming operation time increases
Solution Approach 1:
The patent changes the physical parameters of the channel by introducing stress through stress dielectric layers. This stress modification alters the electron migration rate parameter, enabling faster electron migration during programming operations. By changing the stress parameter rather than extending the electric field maintenance time, the patent achieves improved electron migration without increasing programming operation time.
3Speed
If stress is applied to the channel region to improve carrier mobility, then the carrier mobility improves, but the device structure becomes more complex
Solution Approach 1:
The patent merges the stress application function with existing structural elements. The stress dielectric layers are integrated into the groove structures that are already part of the device architecture, and the stress function is combined with the electrical isolation function of dielectric layers. This merging approach enables stress application to improve carrier mobility without significantly increasing device complexity, as the stress structures are integrated into existing process steps and structural frameworks.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly improves the reading and writing performance of flash memory cells by increasing stress in the channel region, thereby enhancing electron implantation efficiency without additional process or time costs, leveraging existing etching processes.
Implementation Method 1
performing annealing to transfer the stress of the stress dielectric layer to the channel region
Implementation Method 2
performing annealing to transfer the stress of the stress dielectric layer to the channel region
Implementation Method 3
etching the semiconductor substrate to form a groove alongside the gate structure
Implementation Method 4
applying a stress dielectric layer within this groove, followed by annealing to transfer stress laterally onto the channel region, enhancing carrier mobility
Data Source
AI summary
The present application discloses a method for manufacturing a semiconductor device, which includes the following steps: step 1: forming first gate structures on a semiconductor substrate; step 2: performing a first etching process to etch the semiconductor substrate on at least one side of each first gate structure to a certain depth and form a first groove; step 3: performing a stress memorization process, including step 31: forming a stress dielectric layer, the stress dielectric layer covering a peripheral surface of each first gate structure and being filled in the first groove; step 32: performing annealing to transfer the stress of the stress dielectric layer to a channel region; step 33: removing the stress dielectric layer. The present application can increase the effect of transferring the stress of the stress dielectric layer to the channel region, thereby increasing the mobility of channel carriers.