Flash Memory Error Correction via Sub-Sector Segmentation
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Solution Overview
Problem
Flash memory devices face issues with data retention and endurance due to charge loss and gain, leading to widened threshold voltage distributions and increased errors in data read from memory cells, especially as the number of data bits stored in a memory cell increases.
Innovation Solution
A data processing method for flash memory systems that involves judging the correctness of initially read data, re-reading data using newly determined read voltages, collecting error-free sub-sectors based on EDC data, and correcting errors using ECC data, thereby minimizing erroneous bits and improving data integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If more data bits are stored in each memory cell, then storage capacity is improved, but threshold voltage distribution widens and error rate increases
Solution Approach 1:
The memory cell data is divided into multiple sub-sectors, and error correction is performed separately for each sub-sector. This segmentation allows the system to handle errors more effectively in high-density storage by treating smaller units independently, thereby maintaining reliability as storage capacity increases.
Solution Approach 2:
The patent combines multiple error correction techniques (EDC for error detection and ECC for error correction) to create a composite error correction system. This composite approach provides enhanced reliability for high-capacity memory cells by leveraging the strengths of different correction methods.
2Device complexity
If conventional ECC blocks are used for error correction, then device complexity is kept low, but error correction capability is insufficient for multi-bit errors
Solution Approach 1:
Error correction is performed at the sub-sector level rather than treating the entire data block as one unit. This segmentation enables the system to correct multiple bit errors that would overwhelm a conventional ECC block, while keeping the complexity of each individual correction unit manageable.
Solution Approach 2:
The patent introduces an intermediary error detection and correction stage that processes data before it reaches the final ECC block. This intermediary layer filters and pre-corrects errors, reducing the burden on the conventional ECC block and enabling the system to handle more severe error conditions.
Data Source
AI summary
A data processing method of a memory system including a flash memory, which includes judging whether data initially read from a selected page of the flash memory is correctable. If the initially read data is judged not to be correctable, the data is newly read from the selected page based upon each of newly determined read voltages. Thereafter, error-free sub-sectors of the newly read data are collected based upon EDC data corresponding to the initially read data. The data of the error-free sub-sectors are then corrected based upon ECC data corresponding to the initially read data.