Flash Memory Subsystem Parallel Data Transfer Architecture
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Solution Overview
Problem
Current FLASH devices face limitations in achieving high data transfer rates due to their architecture, which restricts the Bus Data Rate to be equal to the Data Rate of individual FLASH devices, failing to meet the demands of modern applications for faster data access and transfer.
Innovation Solution
The proposed solution involves a FLASH memory sub-system architecture that utilizes multiple FLASH devices connected through a switching mechanism, where the system Bus Data I/O lines and Control lines are connected via receivers, latches, and drivers, allowing for a multiplicity of cycles with each cycle divided into two periods, enabling data transfer at twice the rate of individual devices by alternating data access between devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple FLASH devices are connected to increase data transfer rate, then the system bandwidth increases, but the device complexity increases due to switching mechanisms and control logic
Solution Approach 1:
The patent divides the memory system into multiple independent FLASH devices, each operating at their native data rate. The memory space is segmented across these devices, allowing parallel data transfer while maintaining individual device simplicity. This segmentation enables the system to achieve higher aggregate bandwidth without forcing individual devices to operate at higher speeds.
Solution Approach 2:
The patent introduces a switching mechanism as an intermediary component that manages data flow between multiple FLASH devices and the system bus. This switching mechanism, along with associated control logic, coordinates access to multiple devices, enabling high-speed data transfer by arbitrating between devices and managing the complexity externally rather than within each device.
2Speed
If the speed of individual FLASH devices is increased to meet high data rate requirements, then the data transfer rate improves, but the manufacturing difficulty and cost increase
Solution Approach 1:
The patent merges multiple standard-speed FLASH devices into a single high-performance memory subsystem. By combining several devices that each operate at their native, easily manufacturable speeds, the system achieves the equivalent performance of a single high-speed device without the manufacturing challenges associated with producing faster individual FLASH devices.
3Productivity
If multiple FLASH devices are used to increase bandwidth, then the overall memory capacity and data rate improve, but the control and switching logic complexity increases
Solution Approach 1:
The patent implements dynamic control mechanisms that adaptively manage data flow between multiple FLASH devices. The switching logic dynamically routes data based on device availability, data transfer state, and system requirements. This dynamic approach allows the system to optimize bandwidth utilization while managing control complexity through flexible, state-dependent decision-making rather than static complex routing.
Data Source
AI summary
A Flash memory system includes N flash devices, where N is an integer, each flash device having a flash device interface consisting of a control signal line, a R/B signal line, and a I/O signal line, and wherein each flash device has an operating speed of s. A logic block is connected to each flash device interface, and is further connected to a controller which whose interfaces also has a control signal line, a R/B signal line, and a I/O signal line, so that controller operates at an operating speed of N times s, and wherein the logic block controls each flash device simultaneously.