Flash Memory Switch Instruction Circuitry for Algorithm Modification
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Solution Overview
Problem
Current flash memories face challenges in modifying complex algorithm flows due to their read-only memory (ROM) structure, which restricts the ability to change embedded algorithms without significant changes in mask sets, leading to inefficiencies in managing technological variations and correcting design bugs.
Innovation Solution
The introduction of switch instruction circuitry that allows the microcontroller to receive instructions from either the ROM or external t-latches, enabling the testing and implementation of new algorithm flows without altering the existing silicon, thereby allowing for flexible modification of algorithm routines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If instructions are stored in ROM for executing embedded algorithms, then area occupation is reduced and access speed is improved, but the ability to modify algorithm flows is lost requiring mask set changes
Solution Approach 1:
The patent segments the instruction storage into two parts: a ROM containing the base algorithm and a separate programmable fuse array containing modifiable instructions. The microcontroller can selectively execute instructions from either the ROM or the fuse-array, allowing modification of algorithm flows without changing the ROM content or requiring mask set changes.
Solution Approach 2:
The patent introduces an intermediary component - the programmable fuse array - that acts as a mediator between the fixed ROM and the microcontroller. This fuse-array can override or modify ROM instructions during execution, enabling algorithm flow changes without altering the ROM or requiring new mask sets.
2Adaptability or versatility
If programmable fuses are used to alter critical circuits and match technology parameters, then adaptability is improved, but area cost increases due to required array organization and dedicated programming algorithm
Solution Approach 1:
The patent makes the programmable fuse-array multi-functional: it can both match technology parameters by altering critical circuits and modify algorithm flows by overriding ROM instructions. This universal component replaces the need for separate dedicated programming algorithms and reduces overall area cost by consolidating functions.
Solution Approach 2:
The patent merges the technology parameter adjustment function and the algorithm modification function into a single programmable fuse-array structure. This combination eliminates the need for separate array organizations and dedicated programming algorithms, thereby reducing area cost while maintaining adaptability.
3Adaptability or versatility
If an embedded RAM is introduced to store algorithm instructions during testing, then flexibility to check flow modifications is improved, but area cost increases due to RAM core and controller routines
Solution Approach 1:
The patent uses programmable fuses that can be programmed once and then remain fixed, replacing the need for a reusable RAM structure. While fuses are not erasable like RAM, they provide sufficient flexibility for testing and algorithm modification without requiring the complex RAM core and controller routines that would increase area cost.
Data Source
AI summary
A flash memory includes input/output buffers, a memory array having memory cells coupled to the input/output buffers, and row and column decoders, and a voltage-generator circuit coupled to the row and column decoders. A microcontroller is coupled to the command user interface. Switch-instruction circuitry selectively provides instructions to the microcontroller from the read-only memory and from off chip through on-board t-latches coupled to the input/output buffers under control of a command user interface.