Flash Memory Switch Unit Stabilizes Wordline Voltage
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Solution Overview
Problem
Flash memory devices, particularly NOR type, face reliability issues due to unstable wordline voltages caused by parasitic capacitance, leading to increased voltage levels during repeated read operations, which can compromise data read operations.
Innovation Solution
A flash memory device with a switch unit that receives wordline and initialization voltages, selectively outputs these voltages through a switching operation, including providing an initialization voltage after the highest wordline voltage to stabilize the output node and prevent voltage increase, using a control circuit to manage the switching signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If wordline voltage is continuously generated and retained during standby and read operations, then read operation speed is improved, but voltage stability deteriorates due to parasitic capacitance accumulation
Solution Approach 1:
The patent implements periodic initialization of the output node by switching in the initialization voltage at specific intervals during read operations. This periodic action resets the parasitic capacitance accumulation, preventing voltage drift while maintaining overall system functionality. The initialization voltage is applied in a periodic manner to counteract the continuous voltage buildup caused by retained wordline voltage.
Solution Approach 2:
The patent temporarily discards the retained wordline voltage by switching in the initialization voltage to reset the output node voltage. This allows the system to recover from the harmful effect of parasitic capacitance accumulation by periodically clearing the stored charge, then returning to the retained voltage state for subsequent read operations.
2Loss of time
If wordline voltage is generated in advance for high-speed read operations, then access time is reduced, but voltage level control becomes difficult due to parasitic capacitance
Solution Approach 1:
The patent uses the initialization voltage switching mechanism as a feedback control method. By monitoring the need for voltage reset and applying initialization voltage accordingly, the system maintains precise voltage level control despite the presence of parasitic capacitance. The feedback loop ensures that voltage levels remain within acceptable ranges while maintaining fast access times.
Solution Approach 2:
The periodic application of initialization voltage serves to reset the parasitic capacitance at controlled intervals, ensuring that voltage levels remain stable and predictable. This periodic intervention prevents uncontrolled voltage drift while maintaining the advantage of pre-generated wordline voltages for fast access.
3Adaptability or versatility
If multiple wordline voltages are sequentially switched for MLC read operations, then multi-bit data reading is enabled, but voltage stability deteriorates due to repeated switching and parasitic capacitance
Solution Approach 1:
The initialization voltage acts as an intermediary element between sequential wordline voltage switches. By introducing this intermediate voltage state, the system can reset the output node between different wordline voltage applications, preventing parasitic capacitance from causing voltage instability during multi-bit read operations.
Solution Approach 2:
During MLC read operations involving multiple wordline voltages, the initialization voltage is periodically applied to reset the parasitic capacitance between voltage transitions. This periodic intervention ensures that each wordline voltage application starts from a known baseline, maintaining voltage stability throughout the multi-bit reading process.
Data Source
AI summary
Provided is a flash memory device including a wordline voltage generating unit, a switch unit, a row decoder and a control circuit. The wordline voltage generating unit generates at least one wordline voltage for read operations of a multi-level cell in the flash memory device. The switch unit receives the at least one wordline voltage and an initialization voltage, and selectively outputs the at least one wordline voltage and the initialization voltage through a switching operation. The row decoder operates the wordline of the multi-level cell based on an output of the switch unit. The control circuit provides at least one control signal to the switch unit, which outputs the initialization voltage in at least one section of the read operation in response to the at least one control signal.