NAND Flash Memory Translation Table Segmentation
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Solution Overview
Problem
In NAND-type flash memory systems, the size of the logical-to-physical translation table is large, which increases costs and reduces the efficiency of error correction, as it is needed to map logical block addresses to physical block addresses across multiple semiconductor memory chips.
Innovation Solution
A memory system with a first table that stores defect information for each block in a matrix format, allowing for efficient selection of blocks for writing and reading data, and a second table that maps logical block addresses to channel and page numbers, reducing the need for extensive translation and error correction mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a conventional logical-to-physical translation table is used to map logical block addresses to physical block addresses across multiple semiconductor memory chips, then the mapping function is achieved, but the table size becomes large, increasing costs and reducing error correction efficiency
Solution Approach 1:
The patent divides the conventional single large logical-to-physical translation table into two separate tables: a first table that maps logical block addresses to channel and page numbers, and a second table that maps physical block addresses to channel and page numbers. This segmentation reduces the size of each individual table while maintaining the complete mapping functionality, thereby reducing costs and improving error correction efficiency without sacrificing the ability to map logical block addresses to physical block addresses across multiple semiconductor memory chips
2Measurement precision
If a large logical-to-physical translation table is used to ensure complete address mapping, then address translation accuracy is maintained, but the system complexity and cost increase
Solution Approach 1:
The patent segments the address translation process into two stages using two separate tables. The first table translates logical block addresses to intermediate channel and page numbers, while the second table translates physical block addresses to the same intermediate channel and page numbers. This segmentation maintains address translation accuracy by preserving all necessary mapping information while reducing the complexity and size of individual tables, thereby lowering system costs and improving manageability
Data Source
AI summary
According to an embodiment, a memory system includes semiconductor memories each having a plurality of blocks; a first table; a receiving unit; a generating unit; a second table; and a writing unit. The first table includes a plurality of memory areas each associated with each block and in each of which defect information is stored. The generating unit generates a set of blocks by selecting one block to which data are to be written in each semiconductor memory based on an index number indicating one of a plurality of rows in the first table and the first table. In the second table, an index number and a channel number are stored for each logical block address in association with one another. When a write command is received by the receiving unit, the writing unit writes data to a block associated with a selected channel number among blocks constituting the set.