Flash Memory Task Scheduling to Reduce Idle Wait Time

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Flash memory devices, particularly NAND flash devices, experience significant wait times due to their serial access nature, leading to idle computation resources as the processing unit waits for execution outcomes during data programming tasks.

Innovation Solution

Implementing a method and apparatus that schedules data-programming tasks by inserting tasks from subsequent batches into the processing of previous batches, reducing idle time by performing tasks between directing engines to perform tasks and receiving their outcomes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the processing unit waits for execution outcomes during data programming tasks, then the flash memory device can complete programming operations, but the processing unit experiences significant wait times and idle computation resources

Engineering Contradiction:
Improveprogramming operation completionVSAvoidwait time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The processing unit performs preliminary actions by initiating subsequent programming tasks before previous tasks complete. The scheduler inserts tasks from subsequent batches into the processing pipeline, allowing the processing unit to prepare and queue next operations while waiting for current operations to finish, thereby reducing idle wait time.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The system maintains continuity of useful action by keeping the processing unit continuously occupied with scheduling and preparing tasks. Instead of idle waiting, the processing unit continuously manages the task pipeline, inserting new tasks into batches and coordinating with the engine, ensuring useful computational activity occurs throughout the programming process.

Inventive Principle:
Principle #20Continuity of useful action

2Device complexity

If the processing unit performs tasks sequentially waiting for outcomes, then task execution is simple, but computation resources remain idle during wait periods

Engineering Contradiction:
Improvetask execution simplicityVSAvoidprocessing unit efficiency
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The task execution process is segmented into distinct batches (i-th batch, (i+1)-th batch) with clear boundaries. The scheduler divides work into manageable task batches that can be independently managed and inserted into the processing pipeline, allowing complex parallel operations to be organized into simple, structured segments that maintain executability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The task scheduling system introduces dynamic behavior by allowing the processing unit to flexibly insert and manage tasks from subsequent batches based on pipeline availability. The scheduler dynamically adjusts task insertion timing and batch composition, transforming the static sequential execution into a dynamic pipeline that adapts to execution conditions while maintaining operational simplicity.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10387076B2Methods for scheduling data-programming tasks and apparatuses using the same
Publication Date: 2019.08.20 SILICON MOTION INC
  • US10387076B2 patent drawing
  • US10387076B2 patent drawing
  • US10387076B2 patent drawing

AI summary

The invention introduces a method for scheduling data-programming tasks, performed by a processing unit, including at least the following steps. At least one task of an (i+1)-th batch is performed between directing an engine to perform a task of an i-th batch and reception of an outcome of the task of the i-th batch.